Ex Parte Datta et al

Board of Patent Appeals and Interferences

Aug 26, 2011

11028378 (B.P.A.I. Aug. 26, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/028,378 01/03/2005 Suman Datta ITL.1226US (P20669) 8862
21906 7590 08/26/2011
TROP, PRUNER & HU, P.C.
1616 S. VOSS ROAD, SUITE 750
HOUSTON, TX 77057-2631
EXAMINER
REAMES, MATTHEW L
ART UNIT PAPER NUMBER
2893
MAIL DATE DELIVERY MODE
08/26/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte SUMAN DATTA, JUSTIN K. BRASK, JACK KAVALIEROS,
MATTHEW V. METZ, MARK L. DOCZY, and ROBERT S. CHAU
____________

Appeal 2009-010756
Application 11/028,378
Technology Center 2800
____________

Before MARC S. HOFF, CARLA M. KRIVAK, and
THOMAS S. HAHN, Administrative Patent Judges.

KRIVAK, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 47-57. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

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STATEMENT OF THE CASE
Appellants’ claimed invention is related “generally to the formation of
quantum well transistors” (Spec. 1:2-3).
Independent claim 47, reproduced below, is representative of the
subject matter on appeal.
47. A method comprising:
forming a quantum well;
forming a barrier layer over said quantum well;
forming a gate dielectric over said barrier layer;
forming a gate electrode over said gate dielectric;
forming a self-aligned source drain;
selectively forming a depletion mode device by forming said
gate dielectric on top of said barrier layer; and
selectively forming an enhancement mode device by forming
said gate dielectric within said barrier layer.

REJECTIONS
The Examiner rejected claims 47-57 under 35 U.S.C. § 112, first
paragraph, as failing to comply with the written description requirement.
The Examiner rejected claims 47-57 under 35 U.S.C. § 112, second
paragraph, as being indefinite.
The Examiner rejected claims 47-49 under 35 U.S.C. § 103(a) based
upon the teachings of Song (US 6,670,652 B2; Dec. 30, 2003), Ng (KWOK
K. NG, COMPLETE GUIDE TO SEMICONDUCTOR DEVICES (2d ed. 2002)), and
Passlack (Matthias Passlack et al., Self-Aligned GaAs p-Channel
Enhancement Mode MOS Heterostructure Field-Effect Transistor, 23 IEEE
ELECTRON DEVICE LETTERS 508 (2002)).
The Examiner rejected claims 50-55 under 35 U.S.C. § 103(a) based
upon the teachings of Song, Ng, Passlack, Uda (US 6,232,159 B1; May 15,
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2001), and Parikh (P. A. Parikh et al., A New FET-Based Integrated Circuit
Technology: The SASSFET, 17 IEEE ELECTRON DEVICE LETTERS 375
(1996)).
The Examiner rejected claims 56 and 57 under 35 U.S.C. § 103(a)
based upon the teachings of Song, Ng, Passlack, Uda, Parikh, and Fu (D. J.
Fu et al., GaN Metal-Oxide-Semiconductor Structures Using Ga-Oxide
Dielectrics Formed by Photoelectrochemical Oxidation, 80 APPLIED
PHYSICS LETTERS 446 (2002)).

ANALYSIS
Rejection under 35 U.S.C. § 112, first paragraph
The Examiner finds claims 47-57 contain subject matter not described
in Appellants’ Specification. With respect to claim 47, the Examiner finds it
is unclear if the claimed invention is a single device including both a
depletion mode and an enhancement mode device or two separate devices.
Appellants’ Specification shows one or the other is made (Ans. 4-5).
Although Appellants are correct that “[o]ne integrated circuit
commonly includes both” depletion mode and enhancement mode devices,
Appellants’ Specification does not support both devices formed on the same
integrated circuit (App. Br. 9). Appellants’ Summary of the Claimed
Subject Matter states that a depletion mode device is shown in Figure 1 and
an enhancement mode device is shown in Figure 10 (App. Br. 7).
Appellants’ Specification states that “a depletion (Figure 1) or enhancement
mode (Figure 10) self-aligned source drain quantum well transistor may be
formed” (Spec. 3:20-22 (emphasis added)). Further, the Brief Description of
the Drawings relates all the drawings back to Figure 1, thus the subsequent
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processing described in Figure 10 states the depletion mode device shown in
Figure 1 is subsequently processed to form an enhancement mode device.
For these reasons, the Examiner is correct in finding Appellants’ claim 47
does not comply with the written description requirement.
It is well settled that the Examiner has the initial burden of producing
reasons that substantiate a rejection based on lack of enablement. In re
Strahilevitz, 668 F.2d 1229, 1232 (CCPA 1982); In re Marzocchi, 439 F.2d
220, 224 (CCPA 1971). Once this is done, the burden shifts to the appellant
to rebut this conclusion by presenting evidence to prove that the disclosure is
enabling. In re Doyle, 482 F.2d 1385, 1392 (CCPA 1973). The Examiner
has met this burden with respect to claim 47 as noted above, and
additionally, with respect to claims 48-57. Appellants have not provided
support for their assertions that, for example, claim 48 does not require a
third gate electrode, but does leave open the possibility of a third gate
electrode and further, some transistors are formed according to claim 47 and
additional transistors are formed according to claim 48 (Reply Br. 2; App.
Br. 9). Appellants have also not provided evidence to rebut the Examiner’s
conclusions. Rather, they have merely made conclusory statements without
identifying support for these statements in the Specification.
Rejection under 35 U.S.C. § 112, second paragraph
The Examiner finds claims 47-57 are indefinite for failing to
particularly point out and distinctly claim the subject matter of Appellants’
invention (Ans. 6-9). With respect to claim 47, Appellants argue, and we
agree, depletion and enhancement mode devices can be on the same product
(i.e., an integrated circuit) (App. Br.10). However, there is nothing in the
claims defining the method as being for a product rather than a single
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transistor. Further, Appellants have not provided where in the Specification
there is support for this allegation.
The test for definiteness under 35 U.S.C. § 112, second paragraph, is
whether “those skilled in the art would understand what is claimed when the
claim is read in light of the specification.” Orthokinetics, Inc. v. Safety
Travel Chairs, Inc., 806 F.2d 1565, 1576 (Fed. Cir. 1986) (citations
omitted). “[I]f a claim is amenable to two or more plausible claim
constructions, the USPTO is justified in requiring the applicant to more
precisely define the metes and bounds of the claimed invention by holding
the claim unpatentable under 35 U.S.C. § 112, second paragraph, as
indefinite.” Ex parte Miyazaki, 89 USPQ2d 1207, 1211 (BPAI 2008)
(precedential).
[T]he patent drafter is in the best position to resolve the
ambiguity in the patent claims, and it is highly desirable that
patent examiners demand that applicants do so in appropriate
circumstances so that the patent can be amended during
prosecution rather than attempting to resolve the ambiguity in
litigation.
Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255 (Fed. Cir.
2008).
By Appellants’ own admission the claims are amenable to more than
one construction (App. Br. 11; “the claim can be read as . . . the gate
electrode . . . be a metal gate electrode or it could be a third gate electrode”).
Thus, claims 47-57 are found indefinite under 35 U.S.C. § 112, second
paragraph.
Rejections under 35 U.S.C. § 103
Because the independent claims are so indefinite that “considerable
speculation as to [the] meaning of the terms employed and assumptions as to
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the scope of such claims” is needed, we do not address the merits of the
Examiner’s rejection under 35 U.S.C. § 103 over the collective teachings of
Song, Ng, Passlack, Uda, Parikh, and Fu. See In re Steele, 305 F.2d 859,
862 (CCPA 1962) (holding that the Examiner and the Board were wrong in
relying on what at best were speculative assumptions as to the meaning of
the claims and basing a prior-art rejection thereon). The merits of the § 103
rejection are therefore not reached as they would, at best, be based on
speculative assumptions as to the scope of the claims.

CONCLUSION
The Examiner did not err in rejecting claims 47-57 under 35 U.S.C.
§ 112, first and second paragraphs.
The merits of the Examiner’s rejections under 35 U.S.C. § 103(a) is
not reached.

DECISION
The Examiner’s decision rejecting claims 47-57 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv)(2010).

AFFIRMED

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