Ex Parte Dahan et al

Board of Patent Appeals and Interferences

Aug 16, 2010

10256642 (B.P.A.I. Aug. 16, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte FRANCK DAHAN, CHRISTIAN ROUSSEL,
ALAIN CHATEAU, and PETER CUMMING
____________

Appeal 2009-005787
Application 10/256,642
Technology Center 2400
____________

Before JOSEPH F. RUGGIERO, MAHSHID D. SAADAT,
and CARLA M. KRIVAK, Administrative Patent Judges.

SAADAT, Administrative Patent Judge.

DECISION ON APPEAL1

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.
Appeal 2009-005787
Application 10/256,642

2
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1, 2, 4, 6, 7, 9, 17, and 19-23, which constitute all the claims pending
in the application as claims 3, 5, 8, 10-16, and 18 have been canceled. We
have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

STATEMENT OF THE CASE
Appellants’ invention relates to a security mechanism for supporting
secure software services. According to Appellants, a secure execution mode
is entered through a unique entry point that allows virtual addressing when a
memory management unit (MMU) is enabled (Spec. ¶¶ [09] – [10]). Claim
1, which is illustrative of the invention, reads as follows:

1. A method of operating a digital system having a
mechanism for a CPU having an instruction execution pipeline to
enter a secure mode of operation, comprising the steps of:

jumping to an entry address at a particular address in an
instruction memory;

executing an activation sequence of a plurality of instructions
beginning at the entry address; and

entering the secure mode of operation only if the activation
sequence of the plurality of instructions is fully executed by the CPU
in a pre-defined order.

The Examiner relies on the following prior art in rejecting the claims:
Kaplan US 6,282,657 B1 Aug. 28, 2001
Ginter US 2002/0048369 A1 Apr. 25, 2002
(filed Sep. 10, 2001)

Appeal 2009-005787
Application 10/256,642

3
Claims 1, 2, 4, and 15 stand rejected under 35 U.S.C. § 102(e) as
being anticipated by Kaplan.2
Claims 6, 7, 9, 17, and 19-23 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Kaplan and Ginter.3
Rather than repeat the arguments here, we make reference to the
Briefs and the Answer for the respective positions of Appellants and the
Examiner.

ISSUE
The Examiner reads the claimed step of “executing an activation
sequence of a plurality of instructions” on Kaplan’s process of comparing
the program counter with address 0x2000 (Ans. 3-4) and concludes that the
comparing process inherently requires execution of a plurality of instructions
(Ans. 8-9). Appellants contend that entry into the kernel mode in Kaplan
depends only on a single instruction, which is different from the claimed
sequence of a plurality of instructions (App. Br. 7). Additionally, Appellants
assert that Kaplan uses a basic comparator that automatically performs the
comparison by hardware within the kernel program (Reply Br. 2-3).

2 The Examiner inadvertently includes canceled claim 15 in the statement of
rejection. Therefore, we consider this rejection to include only claims 1, 2,
and 4.

3 The details of these grounds of rejection are repeated on pages 5-7 of the
Examiner’s Answer. However, the Examiner initially includes only claims
6, 7, 9, and 17 in the rejection and refers to the rejection of claims 19-23 as
having limitations similar to these claims. We take the rejection of claims
19-23 to have been intended to be over Kaplan and Ginter.
Appeal 2009-005787
Application 10/256,642

4
Therefore, the issue is whether the Examiner erred in rejecting claim 1
as anticipated by Kaplan by reading the claimed “executing an activation
sequence of a plurality of instructions” on Kaplan’s process of comparing
the program counter with address 0x2000.

PRINCIPLES OF LAW
A rejection for anticipation requires that the four corners of a single
prior art document describe every element of the claimed invention, either
expressly or inherently, such that a person of ordinary skill in the art could
practice the invention without undue experimentation. See Atlas Powder
Co. v. IRECO, Inc., 190 F.3d 1342, 1347 (Fed. Cir. 1999); In re Paulsen, 30
F.3d 1475, 1478-79 (Fed. Cir. 1994).

ANALYSIS
We disagree with the Examiner’s characterization (Ans. 8-9) of
Kaplan’s process of comparing the program counter address to address
0x2000 as an activation sequence of a plurality of instructions. We find that
while Kaplan may perform other instructions associated with activating the
kernel output and switching to kernel mode (col. 3, ll. 8-23), the only
activation instruction corresponds to comparing the counter address to
address 0x2000. As argued by Appellants (Reply Br. 2-3), the comparison is
performed automatically by hardware within the kernel program fetch
supervisor 8 because Kaplan uses a basic comparator (col. 2, ll. 41-44),
instead of executing an activation sequence of a plurality of instructions as
claimed.
Appeal 2009-005787
Application 10/256,642

5
As discussed above, Kaplan performs the comparison by using a
single comparator without indicating that a plurality of instructions is
executed. Therefore, contrary to the Examiner’s interpretation of the
reference’s teachings (Ans. 9), no sequence or pre-defined order of
instructions is used by the comparator to compare address to a
predetermined address and enter the secure kernel. See also Kaplan at col.
4, ll. 24-29.

CONCLUSION
On the record before us, we find that the Examiner erred in rejecting
claim 1 by reading the claimed step of “executing an activation sequence of
a plurality of instructions” on Kaplan’s process of comparing the program
counter with address 0x2000. Therefore, the 35 U.S.C. § 102 rejection of
claims 1, 2, and 4 as anticipated by Kaplan cannot be sustained.
Additionally, we do not sustain the 35 U.S.C. § 103 rejection of claims 6, 7,
9, 17 and 19-23 over Kaplan and Ginter as the Examiner has not identified
any teachings in Ginter that would have overcome the deficiency discussed
above.

ORDER
The decision of the Examiner rejecting claims 1, 2, 4, 6, 7, 9, 17, and
19-23 is reversed.

REVERSED

Appeal 2009-005787
Application 10/256,642

6
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