Ex Parte Daffron

Board of Patent Appeals and Interferences

Feb 26, 2008

10248785 (B.P.A.I. Feb. 26, 2008)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte CHRISTOPHER JOSEPH DAFFRON
____________

Appeal 2007-3125
Application 10/248,7851
Technology Center 2100
____________

Decided: February 26, 2008
____________

Before JAMES D. THOMAS, HOWARD B. BLANKENSHIP,
and JEAN R. HOMERE, Administrative Patent Judges.

HOMERE, Administrative Patent Judge.

ORDER REMANDING TO THE EXAMINER
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134 from the Examiner’s final
rejection of claims 1 and 2. We have jurisdiction under 35 U.S.C. § 6(b).

1 Filed on Feb. 18, 2003. Appellant is the real party in interest.
1
Appeal 2007-3125
Application 10/248,785

The Invention
Appellant invented a processor that converts pre-compiled or pre-
assembled instruction sequences for complex instruction set computers
(CISC) or reduced instruction set computer (RISC) type machines into
configuration bitmaps that are assembled to create finite state machines.
(Spec. 2.) As depicted in Figure 1, the processor includes an integrated
decoder circuit block (23) that decodes, orders, and parses sequences of the
CISC or RISC type machine instructions fetched from a shared memory.
(Id. 4.) The processor further includes an integrated converter circuit block
(24) that converts the parsed instructions into configuration bitmaps. An
integrated constructor circuit block (25) subsequently assembles the
configuration bitmaps into executable state finite machines that are capable
of executing the computer algorithms at a much faster rate than the
originally targeted RISC or CISC processor. (Id. 2, 4.)
An understanding of the invention can be derived from exemplary
independent claim 1, which reads as follows:
1. A processor that configures and executes finite state machines, that
are dedicated to performing particular computer algorithms, by utilizing both
re-configurable logic, and configuration data that is created by the processor
from decoded Complex Instruction Set Computer (CISC) type or Reduced
Instruction Set Computer (RISC) type machine instruction sequences that
are composed of members of a particular CISC type or RISC type
processor's machine instruction set, and were originally created then stored
in shared memory with the intent of being executed by the said CISC type or
RISC type processor in order to perform the said particular computer
algorithms that are instead being executed by the said configured finite state
machines;

2
Appeal 2007-2336
Application 10/365,855

And wherein the processor comprises:

An integrated array of re-configurable logic elements;

An integrated array of re-configurable registers;

An integrated programmable switch network having operational connections
to every element contained within both the array of re-configurable logic
elements and the array of re-configurable registers;

An integrated memory circuit block;

An integrated decoder circuit block having the functions of dynamically
decoding, re-ordering, and parsing sequences of said CISC or RISC type
machine instructions fetched from shared memory that represent said
particular computer algorithms which were originally intended to be
executed by the said CISC or RISC type processor;

An integrated converter circuit block having the function of dynamically
converting the said decoded and parsed sequences of machine instructions
into newly built configuration bit maps;

An integrated constructer circuit block having the function of constructing
executable finite state machines thru the use of configuration bit maps, that
are created by the said converter circuit block, and the controlling of the
programmable switch network;

An integrated memory bus controller circuit block having the function of
interfacing with an external bus used to access shared memory;

An integrated communication bus controller circuit block having the
function of interfacing with an external bus used to communicate with the
other processors; and

An integrated main controller circuit block having the function of
controlling and coordinating the activities of all said integrated circuit
blocks.

3
Appeal 2007-2336
Application 10/365,855

The Examiner rejected claims 1 and 2 under 35 U.S.C. § 112, first
paragraph, as failing to comply with the enablement requirement.

PRINCIPLES OF LAW
ENABLEMENT
The standard for determining whether the specification meets the
enablement requirement was cast in the Supreme Court decision of Mineral
Separation v. Hyde, 242 U.S. 261, 270 (1916) which postured the question:
Is the experimentation needed to practice the invention undue or
unreasonable? That standard is still the one to be applied. In re Wands,
858 F.2d 731, 737 (Fed. Cir. 1988). Therefore, the test of enablement is
whether one reasonably skilled in the art could make or use the invention
from the disclosures in the patent coupled with information known in the art
without undue experimentation. A patent need not teach, and preferably
omits, what is well known in the art. In re Buchner, 929 F.2d 660, 661 (Fed.
Cir. 1991); Hybritech, Inc. v. Monoclonal Antibodies, Inc., 802 F.2d 1367,
1384 (Fed. Cir. 1986); and Lindemann Maschinenfabrik GMBH v. American
Hoist & Derrick Co., 730 F.2d 1452, 1463 (Fed. Cir. 1984). The test of
enablement is not whether any experimentation is necessary, but whether, if
experimentation is necessary, it is undue. In re Angstadt, 537 F.2d 498, 504
(CCPA 1976). There are many factors to be considered when determining
whether there is sufficient evidence to support a determination that a
disclosure does not satisfy the enablement requirement and whether any
necessary experimentation is “undue.” These factors include, but are not
limited to:
4
Appeal 2007-2336
Application 10/365,855

(A) The breadth of the claims;
(B) The nature of the invention;
(C) The state of the prior art;
(D) The level of one of ordinary skill;
(E) The level of predictability in the art;
(F) The amount of direction provided by the inventor;
(G) The existence of working examples; and
(H) The quantity of experimentation needed to make or use the
invention based on the content of the disclosure. In re Wands, 858 F.2d 731,
737 (Fed. Cir. 1988).
A conclusion of lack of enablement means that, based on the evidence
regarding each of the above factors, the specification, at the time the
application was filed, would not have taught one skilled in the art how to
make and/or use the full scope of the claimed invention without undue
experimentation. In re Wright, 999 F.2d 1557,1562 (Fed. Cir. 1993).

ANALYSIS
Independent claim 1 recites in relevant-part an integrated converter
circuit block for converting decoded and parsed sequences of machine
instructions into newly built configuration bitmaps. (App. Br., Claims
Appendix.) The Examiner submits that, given the very brief description of
the converter provided in paragraph 0014 of Appellant’s Specification, one
of ordinary skill would not be able to reproduce the claimed converter based
on that description alone without undue experimentation. The Examiner
further buttresses his position based on the summary of an informal
5
Appeal 2007-2336
Application 10/365,855

interview during which Appellant allegedly admitted that he was not totally
aware how the converter block would be constructed. Therefore, the
Examiner concludes that claims 1 and 2 fail to comply with the enablement
requirement. (Ans. 13, 15-18.)
As set forth in the Principle of Law section above, the test of
enablement is whether one reasonably skilled in the art could make or use
the invention from the disclosures in the patent coupled with information
known in the art without undue experimentation. The determination that
“undue experimentation” would have been needed to make and use the
claimed invention is not a single, simple factual determination. Rather, it is
a conclusion reached by weighing all the above-noted factual considerations.
In re Wands, 858 F.2d at 737. Since the Examiner’s enablement rejection
fails to weigh these factors to show that the ordinarily skilled artisan would
not be able to make or use the claimed converter block based on Appellant’s
Specification without undue experimentation, this case is not ripe for a
meaningful review. See MPEP § 2164.01, 2164.01(a)). (8th ed., Rev. 6,
Sep. 2007).

V. ORDER
Accordingly, we REMAND this application to the Examiner to:
(1) weigh all factors A through H of In re Wands to show that claims 1 and 2
do not comply with the enablement requirement,
(2) further evaluate Appellant’s reply thereto in accordance with 37 C.F.R.
§ 41.41, and
6
Appeal 2007-2336
Application 10/365,855

(3) for such further actions in accordance with 37 C.F.R. § 41.43,
as may be appropriate.
REMANDED

clj

CHRISTOPHER JOSEPH DAFFRON
4714 N. 111th Dr.
PHOENIX, AZ 85037
7