Ex Parte CraskeDownload PDFPatent Trial and Appeal BoardJun 22, 201612654617 (P.T.A.B. Jun. 22, 2016) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 12/654,617 12/24/2009 73459 7590 06/24/2016 NIXON & V ANDERHYE, P,C 901 NORTH GLEBE ROAD, 11 TH FLOOR ARLINGTON, VA 22203 FIRST NAMED INVENTOR Simon John Craske UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. JRL-550-1228 2924 EXAMINER BIRKHIMER, CHRISTOPHER D ART UNIT PAPER NUMBER 2136 NOTIFICATION DATE DELIVERY MODE 06/24/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): PTOMAIL@nixonvan.com pair_nixon@firsttofile.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte SIMON JOHN CRASKE Appeal2014-005256 Application 12/654,617 Technology Center 2100 Before CAROLYN D. THOMAS, ERIC B. CHEN, and KARA L. SZPONDOWSKI, Administrative Patent Judges. CHEN, Administrative Patent Judge. DECISION ON APPEAL Appeal2014-005256 Application 12/654,617 This is an appeal under 35 U.S.C. § 134(a) from the final rejection of claims 1-10, all the claims pending in the application. We have jurisdiction under 35 U.S.C. § 6(b). We affirm-in-part. STATEMENT OF THE CASE Appellant's invention relates to a data processing apparatus for handling of a wait for event operation. (Abstract.) Claims 1 and 2 are exemplary, with disputed limitations in italics: 1. A data processing apparatus for forming a portion of a coherent cache system, comprising: a master device configured to perform data processing operations, including a wait for event operation causing the master device to enter a power saving mode; a cache coupled to the master device and arranged to store data values for access by the master device when performing said data processing operations; coherency handling circuitry within the cache, and responsive to a coherency request from another portion of the coherent cache system, to detect whether a data value identified by the coherency request is present in the cache, and if so to cause a coherency action to be taken in respect of that data value stored in the cache; and wake event circuitry within the cache, and responsive to the coherency handling circuitry, to locally issue a wake event to the master device if the coherency action is taken; the master device being responsive to the wake event to exit the power saving mode. 2. A data processing apparatus as claimed in Claim 1, wherein: during performance of said data processing operations, the master device is arranged to perform an access operation to access a semaphore stored in shared memory, 2 Appeal2014-005256 Application 12/654,617 the shared memory being shared with at least one further master device within the coherent cache system, and the semaphore being used to maintain an ordering between one or more data processing operations performed by the master device and one or more data processing operations performed by the at least one further master device; performance of the access operation causing a current value of the semaphore to be stored in the cache; and if the current value obtained by the access operation indicates a stall condition, the master device being arranged to perform the wait for event operation. Claims 1, 4, and 8-10 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Appellant's admitted prior art (AAPA) and Bryg (US 6,049,851; Apr. 11, 2000). Claims 2, 3, and 5-7 stand rejected under 35 U.S.C. § 103(a) as unpatentable over AAP A, Bryg, and Handy (JIM HANDY, THE CACHE MEMORY BOOK: THE AUTHORITATIVE REFERENCE ON CACHE DESIGN 140 (2nd ed. 1998)). ANALYSIS § 103 Rejection-AAP A and Bryg We are unpersuaded by Appellant's arguments (App. Br. 7-14; see also Reply Br. 2-8) that the combination of AAP A and Bryg would not have rendered obvious independent claim 1, which includes the limitations "wake event circuitry within the cache, and responsive to the coherency handling circuitry, to locally issue a wake event to the master device if the coherency action is taken" and "the master device being responsive to the wake event to exit the power saving mode." 3 Appeal2014-005256 Application 12/654,617 The Examiner found that the master device of AAP A having a power saving mode of operation, which is woken when a semaphore value changes, corresponds to the limitations "wake event circuitry" (Final Act. 4) and "responsive to the wake event to exit the power saving mode" (see Ans. 3). The Examiner further found that the double cache snoop mechanism of Bryg, having a processor with a central processing unit (CPU) coupled to a cache memory, corresponds to the limitation "circuitry within the cache, and responsive to the coherency handling circuitry, to locally issue a[ n] ... event to the master device if the coherency action is taken" and "the master device being responsive to the ... event." (Final Act. 4--5.) In particular, the Examiner found that "[t]he ... event issued in step 311 ... is also directly dependent on the outcome of step 305 being a YES" and "[t]he coherency action taking from the YES outcome of 305 results in the ... event in step 311." (Ans. 5.) The Examiner concluded that it would have been obvious to combine Bryg and AAP A "because it reduces the stall time due to coherency checks." (Final Act. 5.) We agree with the Examiner. In the "Description of the Prior Art" section (i.e., AAPA), Appellant's Specification admits that "if a master device enters such a power saving mode of operation, it is clearly important to provide a mechanism to enable that master device to be woken when the semaphore value changes, and hence the master device may be able to continue its operation" and "this [wakening] is achieved by arranging for the other master devices in the system to issue a notification over a dedicated path when they update the value of a semaphore." (Spec. 3:7-13.) Furthermore, Appellant's Specification admits that "it is known to employ a cache coherency protocol within the multi-processing system to ensure that if a particular master 4 Appeal2014-005256 Application 12/654,617 device updates a data value held in its local cache, that up-to-date data will be made available to any other master device subsequently requesting access to that data." (Spec. 4:31 to 5:3.) Thus, because AAPA explains that a mechanism for waking master devices is provided when the semaphore value changes, AAP A teaches the limitations "wake event circuitry" and a master device "responsive to the wake event to exit the power saving mode." Bryg "relates to maintaining cache coherency in a uniprocessor or multiprocessor computer architecture." (Col. 1, 11. 11-13.) Bryg explains that "[t]he double cache snoop mechanism ... reduces the average number of cycles that a processor is stalled or locked during a coherency check." (Col. 3, 11. 41--43.) Figure 2 of Bryg illustrates a block diagram of processor 10 in a multiprocessor computer architecture, including CPU 11, processor cache 13, and gating circuit 30 for controlling propagation of a CPU signal. (Col. 5, 11. 18-24.) Figure 3 of Bryg illustrates a flow diagram for a snooping sequence in a multiprocessor computer architecture. (Col. 4, 11. 11-14.) In particular, in one exemplary snooping sequence illustrated in Figure 3, "[i]f the snoop sequence returns a hit (305) [i.e., "YES" in Figure 3], then the CPU is relocked (306) and the cache is reread (307)" (col. 5, 11. 64--66) and "[i]f the reread returns a hit (309) [i.e., "YES" in Figure 3], then the cache is written (310), after which the CPU [11] is unlocked (311) and processor [ 1 OJ operation is allowed to continue (312)" (col. 6, 11. 4--6). Because Bryg explains that processor 10 includes CPU 11 that is unlocked after cache 10 is read, reread, and written (i.e., cache coherency is maintained), Bryg teaches the limitations "circuitry within the cache, and responsive to the coherency handling circuitry, to locally issue 5 Appeal2014-005256 Application 12/654,617 [an] ... event to the master device if the coherency action is taken" and "the master device being responsive to the ... event." A person of ordinary skill in the art would have recognized that incorporating the double cache snoop mechanism of Bryg, as illustrated in Figure 3, with the mechanism for wakening master devices of AAPA would improve AAP A by providing the advantage of reducing the number of cycles of a coherency check. See KSR Int 'l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007) ("[I]f a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill."). This combination would result in utilizing the step of unlocking CPU 11 of Bryg to also provide a wakening mechanism for master devices of AAP A, and thus teaches the limitation "wake event." Thus, we agree with the Examiner (Final Act. 5) that modifying the mechanism for wakening master devices of AAP A to incorporate the double cache snoop mechanism of Bryg would have been obvious. First, Appellant argues "the text starting at page 3, line 18 of the application is not AAP A." (Reply Br. 2 (emphasis omitted).) However, page 1, line 7 to page 6, line 8 of Appellant's Specification is the "Description of the Prior Art" section. In general, the content of this section includes "paragraph( s) describing ... the state of the prior art or other information disclosed known to the applicant, including references to specific prior art or other information where appropriate." MPEP § 608. 01 ( c). According! y, the entire content this "Description of the Prior Art" section constitutes admitted prior art. See In re Nomiya, 509 F .2d 566, 6 Appeal2014-005256 Application 12/654,617 571 (CCPA 1975) ("By filing an application containing Figs. 1 and 2, labeled prior art, ipsissimis verbis ... appellants have conceded what is to be considered as prior art in determining obviousness of their improvement."). Second, Appellant argues "[a] key fact, ignored by the Examiner, is that the technique described in the relied-on AAP A has nothing to do with caches or cache coherency" and "[t]his is important because claim 1 is directed to a cache-based system where cache coherency is a central aspect of the claim." (App. Br. 8 (emphasis omitted); see also Reply Br. 5.) Contrary to Appellant's arguments, AAPA states that "it is known to employ a cache coherency protocol within the multi-processing system to ensure that if a particular master device updates a data value held in its local cache, that up-to-date data will be made available to any other master device subsequently requesting access to that data." (Spec. 4:31 to 5:3.) Third, Appellant argues: [ t ]he applied AAP A's wake event mechanism for waking a master device from a power saving mode of operation involves the issuance of a notification over a dedicated path from a second master device when that second master device has finished with the shared resource to wake up the first master device (App. Br. 9-10) and the "Unlock CPU mechanism [of Bryg] has nothing to do with issuing a wake event to the master device to cause the master device to exit a power saving mode, where the master device enters the power saving mode on execution of a wait for event (WFE) operation" (App. Br. 10; see also Reply Br. 6-7). However, the Examiner cited to AAPA for the general teaching of the limitation "wake event circuitry" (Final Act. 4) and cited Bryg for teaching the limitation "event circuitry within the cache, and responsive to the coherency handling circuitry, to locally issue a[ n] ... 7 Appeal2014-005256 Application 12/654,617 event to the master device if the coherency action is taken" (Final Act. 4-5). Moreover, the rejection of claim 1 is based on the combination of AAP A and Bryg, and Appellant cannot show non-obviousness by attacking references individually. See In re Keller, 642 F.2d 413, 426 (CCPA 1981). Fourth, Appellant argues "the AAPA does not teach 'locally' issuing a wake event to the master device if the coherency action is taken" and "[i]nstead, the wake event mechanism in the AAP A has the second master device issuing a wake up notification over a dedicated path to the first master device when the second master device has finished with a shared resource." (Reply Br. 6.) However, the Examiner cited to Bryg for teaching the limitation "locally issue [an] ... event" (Ans. 5) and the Examiner cited to AAP A for the general teaching of the limitation "wake event circuitry" (Final Act. 4). Again, Appellant cannot show non-obviousness by attacking references individually. Fifth, Appellant argues that "the unlocking at step 311 in Figure 3 in Bryg occurs irrespective of whether there is a hit at step 309 (both the 'No' and 'Yes' paths ultimately lead to the CPU unlocking at step 311 ), and hence, irrespective of whether any coherency action is taken." (App. Br. 12.) However, as found by the Examiner, the limitation "to locally issue a[n] ... event to the master device ifthe coherency action is taken," as recited in claim 1, is broad enough to encompass unlocking CPU 11 of Bryg when the reread returns a hit, and the claim does not exclude unlocking CPU 11 when the reread does not return a hit. (Ans. 5.) Last, Appellant argues "it was the inventor who recognized that in a coherent cache system, coherency requests continue to be serviced even when an associated master device enters the power saving mode" (App. 8 Appeal2014-005256 Application 12/654,617 Br. 13) and "[b]ased on that recognition, the inventor realized that a coherency action taken in response to processing a coherency request within the cache provides a useful indication for the master device to exit from the power saving mode and check whether the shared resource is now available" (id. at 13-14; see also Reply Br. 3--4). However, other than making conclusory statements, Appellant has not presented any persuasive evidence to support the arguments that "it was the inventor who recognized that in a coherent cache system, coherency requests continue to be serviced even when an associated master device enters the power saving mode." Arguments of counsel cannot take the place of factually supported objective evidence. See, e.g., In re Huang, 100 F.3d 135, 139--40 (Fed. Cir. 1996). Thus, we agree with the Examiner that the combination of AAP A and Bryg would have rendered obvious independent claim 1, which includes the limitations "wake event circuitry within the cache, and responsive to the coherency handling circuitry, to locally issue a wake event to the master device if the coherency action is taken" and "the master device being responsive to the wake event to exit the power saving mode." Accordingly, we sustain the rejection of independent claim 1 under 35 U.S.C. § 103(a). Claims 4 and 8 depend from claim 1, and Appellant has not presented any substantive arguments with respect to these claims. Therefore, we sustain the rejection of claims 4 and 8 under 35 U.S.C. § 103(a), for the same reasons discussed with respect to independent claim 1. Independent claims 9 and 10 recite limitations similar to those discussed with respect to independent claim 1, and Appellant has not presented any substantive arguments with respect to these claims. We 9 Appeal2014-005256 Application 12/654,617 sustain the rejection of claims 9 and 10 for the same reasons discussed with respect to claim 1. § 103 Rejection-AAPA, Bryg, and Handy We are persuaded by Appellant's arguments (App. Br. 15-17) that the combination AAP A, Bryg, and Handy would not have rendered obvious dependent claim 2, which includes the limitation "the master device is arranged to perform an access operation to access a semaphore stored in shared memory ... performance of the access operation causing a current value of the semaphore to be stored in the cache." The Examiner found the combination of AAP A, Bryg, and Handy teaches the limitation "the master device performing an access operation in order to access a semaphore stored in shared memory ... a current value of the semaphore to be stored in the cache," as recited in claim 2. (Final Act. 11-12.) In particular, the Examiner acknowledged that "AAPA in view of Bryg may not specifically disclose the limitation of the shared memory being cache memory" (id. at 12) and relied upon "AAP A ... to teach the semaphore ... stored in a shared memory location allowing multiple devices to access the memory location bases on the semaphore value" and "[H]andy ... to teach a shared memory location in a computer system is cache memory" (Ans. 6). We do not agree. AAP A states that "[i]n order to control access to various shared resources within the shared memory, it is known to use semaphores" in which "[a] semaphore is a protected variable or abstract data type used to restrict access to a shared resource in a multi-processing system 10 Appeal2014-005256 Application 12/654,617 environment." (Spec. 1 :20-23.) Handy explains that a cache can be shared by multiple CPUs. (P. 140; see also Fig. 4.6.) Claim 1 recites "a cache" and dependent claim 2 further recites a "shared memory" as a separate element. Although the Examiner cited AAP A for "the semaphore ... stored in a shared memory" and cited Handy for "a shared memory location in a computer system [that] is cache memory" (Ans. 6), the Examiner has not identified a feature in the prior art that corresponds to "causing a current value of the semaphore to be stored in the cache," particularly when the Examiner's modification of AAPA appears to be substituting the shared memory of AAP A with the cache of Handy (Final Act. 12). Moreover, the Examiner's proposed modification apparently substitutes the shared memory of AAP A with the cache of Handy, when claim 1 already recites a "cache." Accordingly, we are persuaded by Appellant's arguments that: (i) the Examiner's statement "[h]owever AAPA may not specifically disclose the limitation of the shared memory being cache memory" is not recited in claim 2; (ii) "[t]he shared memory is recited as a separate feature to 'the cache coupled to the master device" (App. Br. 16); and (iii) "this section [page 1, line 20 to page 2, line 23 of the Specification] makes no reference to 'the cache' referred to in the claims and does not describe performance of the access operation causing a current value of the semaphore to be stored in the cache" (id. at 16-17). Therefore, we do not sustain the rejection of dependent claim 2 under 35 U.S.C. § 103(a). Claims 3 and 5-7 depend from dependent claim 2. We do not sustain the rejection of claims 3 and 5-7 under 35 U.S.C. § 103(a) for the same reasons discussed with respect to dependent claim 2. 11 Appeal2014-005256 Application 12/654,617 DECISION The Examiner's decision rejecting claims 1, 4, and, 8-10 is affirmed. The Examiner's decision rejecting claims 2, 3, and 5-7 is reversed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv). AFFIRMED-IN-PART 12 Copy with citationCopy as parenthetical citation