Ex Parte Cook

Board of Patent Appeals and Interferences

Jul 27, 2009

09946097 (B.P.A.I. Jul. 27, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte B. SCOTT COOK
____________

Appeal 2009-004875
Application 09/946,097
Technology Center 2100
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Decided:1 July 27, 2009
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Before LANCE LEONARD BARRY, JOHN A. JEFFERY, and
ST. JOHN COURTENAY III, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1 and 4-29. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
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STATEMENT OF THE CASE
Appellant invented a chip with a distributed bus architecture that
enables communicating packets of data between multiple source/destination
nodes. Each node monitors a connecting path (e.g., a bus) for receipt of a
data packet. Upon receipt, the node then determines whether the packet is
addressed to that node. If so, the node takes the data from the packet.
Otherwise, the node transmits the packet to a neighboring node.2 Claim 1 is
illustrative:
1. A chip, comprising:

a plurality of nodes on the chip, each of the plurality of nodes are
coupled to one another using a distributed bus architecture that enables a
packet of data to be communicated between the nodes on the chip, wherein
each of the plurality of nodes comprises:

a lower level processor that implements an access control protocol to
build and send data packets to another node and receive data packets on the
distributed bus by determining whether the received packet of data is
addressed to the node and by determining whether the packet of data can be
overwritten; and

a higher-level circuit that performs a specific operation with data
taken from the packet of data received by said lower level processor on a
connecting path from another lower level processor.

The Examiner relies on the following as evidence of unpatentability:
Benzimra US 5,812,547 Sept. 22, 1998
Raatikainen US 5,886,992 Mar. 23, 1999
Hartmann US 5,974,487 Oct. 26, 1999

2 See generally Abstract; Spec. 15-20; Fig. 7.
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1. The Examiner rejected claim 24 under 35 U.S.C. § 102(b) as
anticipated by Hartmann. Ans. 3.
2. The Examiner rejected claims 1, 4, 6-18, 20-23, and 25-29 under 35
U.S.C. § 103(a) as unpatentable over Hartmann and Raatikainen.
Ans. 3-13.
3. The Examiner rejected claims 5 and 19 under 35 U.S.C. § 103(a) as
unpatentable over Hartmann, Raatikainen, and Benzimra. Ans. 13-14.
Rather than repeat the arguments of Appellant or the Examiner, we
refer to the Briefs and the Answer3 for their respective details. In this
decision, we have considered only those arguments actually made by
Appellant. Arguments which Appellant could have made but did not make
in the Briefs have not been considered and are deemed to be waived. See 37
C.F.R. § 41.37(c)(1)(vii).

THE ANTICIPATION REJECTION
Regarding claim 24, the Examiner finds that Hartmann discloses a
method for making a chip with “nodes” (modules 210) connected via
connecting paths on which the nodes can write and receive data packets to
and from each node as claimed. Ans. 3.
Appellant argues that Hartmann fails to disclose data packets, but
rather an unspecified form of “data.” Appellant adds that Hartmann’s
modules also do not send or receive data from each node, but rather data is
routed to switchpoints. App. Br. 21; Reply Br. 18.

3 Throughout this opinion, we refer to (1) the Appeal Brief filed April 5,
2007; (2) the Examiner’s Answer mailed July 23, 2007; and (3) the Reply
Brief filed September 24, 2007.
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The issue before us, then, is as follows:

ISSUE
Under § 102, have Appellant shown that the Examiner erred in
rejecting claim 24 by finding that Hartmann connects plural nodes on a chip
using connecting paths on which each node can write data packets to, and
receive data packets from, each node?

FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence:
Hartmann
1. Hartmann discloses a computer chip 100 with a data transfer
network using a mesh of rings topology for interconnecting plural modules
210A-210I. Buses 230 provide an electrical path for data communications
between the modules via switchpoints 240A-240L. Hartmann, col. 3, l.
23 − col. 4, l. 51; Fig. 2A. This on-chip network is shown in Figure 2A
reproduced below:
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Hartmann’s On-Chip Network in Figure 2A

2. Each module may couple to a bus 230, switchpoint 240, and/or
another module 210 using bus interface logic 410 either incorporated in the
module or as part of a communications port between the module and the bus.
Hartmann, col. 6, ll. 46-51; Figs. 2A and 4.
3. Each switchpoint routes data from a source link or bus to a
destination link or bus so that the modules can communicate with each other
through the links or buses and switchpoints. Hartmann, col. 1, ll. 54-57.
4. Module 210 transmits and receives data from other modules via the
module’s input/output buffer 420 coupled to bus interface logic 410 and
logic/memory elements 430. The module can comprise other components
with or without other couplings. Hartmann, col. 6, ll. 55-60; Fig. 4.

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Appellant’s Disclosure
5. According to Appellant’s Specification, “the packets of data 704
can be thought of in terms of information packets traveling from a source
node to a destination node. The information packet is similar to the data
packets that flow through telecommunication networks.” Spec. 17:19-22.
6. Each packet of data 704 includes a header section 712 and a
payload section 714. The header section contains address and control
sections, respectively. Spec. 18:1-17.

PRINCIPLES OF LAW
Anticipation is established only when a single prior art reference
discloses, expressly or under the principles of inherency, each and every
element of a claimed invention as well as disclosing structure which is
capable of performing the recited functional limitations. RCA Corp. v. Appl.
Dig. Data Sys., Inc., 730 F.2d 1440, 1444 (Fed. Cir. 1984); W.L. Gore &
Assoc., Inc. v. Garlock, Inc., 721 F.2d 1540, 1554 (Fed. Cir. 1983).
During patent examination, a claim is given its broadest reasonable
construction “in light of the specification as it would be interpreted by one of
ordinary skill in the art.” In re Am. Acad. Of Sci. Tech. Ctr., 367 F.3d 1359,
1364 (Fed. Cir. 2004). However, such an interpretation must not import
limitations from the Specification into the claims. “[A]lthough the
specification often describes very specific embodiments of the invention, we
have repeatedly warned against confining the claims to those embodiments. .
. . [C]laims may embrace ‘different subject matter than is illustrated in the
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specific embodiments in the specification.’” Phillips v. AWH Corp., 415
F.3d 1303, 1323 (Fed. Cir. 2005) (en banc) (citations and internal quotation
marks omitted).

ANALYSIS
Based on the record before us, we find no error in the Examiner’s
anticipation rejection of claim 24. Although Hartmann’s modules (nodes)
communicate with each other via switchpoints located on the buses between
each module (FF 1 and 3), the scope of the claim simply does not preclude
data transfer between nodes via these switchpoints. That is, while data
would pass through the switchpoints when traveling from one module to
another, data would ultimately be transferred between the modules
themselves. See FF 1, 3, and 4. In any event, Hartmann also indicates that
modules can connect to each other as an alternative to connecting to a
switchpoint. See FF 2 (noting that each module may couple to a bus,
switchpoint, and/or another module) (emphasis added).
We also see no reason why a packet cannot constitute “a unit of data
sent over a network” as the Examiner indicates (Ans. 15), particularly since
the term “packet” is not defined in the Specification. Nor has Appellant
provided any evidence on this record to rebut this construction. Although
Appellant’s Specification does describe a particular form of packet
containing header and payload sections respectively (FF 5-6), this
description hardly defines the term so as to limit its construction. We
therefore decline to import this description into the claims. See Phillips, 415
F.3d at 1323 (“[C]laims may embrace different subject matter than is
illustrated in the specific embodiments in the specification.”).
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While Hartmann does not specify the nature of the “data”
communicated between modules and switchpoints (see FF 3-4), this data
would nonetheless be at least a unit of data sent over a network and therefore
reasonably comport with the Examiner’s construction of a data “packet.”
For the foregoing reasons, Appellant has not persuaded us of error in
the Examiner’s rejection of claim 24. Therefore, we will sustain the
Examiner’s rejection of that claim.

THE OBVIOUSNESS REJECTION OVER HARTMANN AND RAATIKAINEN
Regarding independent claim 1, the Examiner finds that Hartmann
discloses all of the claimed subject matter except for a single ring distributed
bus architecture where each node comprises (1) a lower-level processor
implementing an access control protocol, and (2) a higher-level circuit as
claimed. The Examiner, however, relies on Raatikainen for this feature in
concluding the claim would have been obvious. Ans. 3-5. The Examiner
reasons that by modifying Hartmann’s on-chip network in light of
Raatikainen’s ring bus architecture, there would be no need for the
centralized switchpoint 340 and mesh of rings in the chip as shown in Figure
3A of Hartmann since the nodes could simply communicate with each other
via a single ring distributed ring bus architecture. Ans. 16-18.
Appellant argues that Hartmann does not disclose a distributed bus
architecture where each node has a lower-level processor and higher-level
circuit as claimed, but rather merely discloses a hub technology
interconnecting multiple modules. App. Br. 10-11. Appellant also reiterates
that Hartmann does not disclose a packet of data as claimed. App. Br. 11.
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Appellant further contends that the Examiner’s reliance on
Raatikainen is misplaced since its multiple “nodes” are not on a single
integrated circuit, but rather are complex hardware routers designed for use
in LANs or WANs and have multiple cards and circuits. App. Br. 11-12;
Reply Br. 6-7. According to Appellant, it would be inoperable to implement
Raatikainen’s ring bus architecture on Hartmann’s single chip as the
Examiner proposes in view of Raatikainen’s teaching of using such ring nets
with coaxial or twisted pair cables over a LAN or WAN of 1000 meters.
App. Br. 15-16; Reply Br. 8.
The issues before us, then, are as follows:

ISSUES
(1) Under § 103, has Appellant shown that the Examiner erred in
rejecting claim 1 by finding that Hartmann and Raatikainen collectively
teach or suggest a chip with a distributed bus architecture enabling a data
packet to be communicated between nodes on the chip where each node
comprises (1) a lower-level processor implementing an access control
protocol, and (2) a higher-level circuit performing a specific operation with
data taken from the packet as claimed?
(2) Is the Examiner’s reason to combine the teachings of Hartmann
and Raatikainen supported by articulated reasoning with some rational
underpinning to justify the Examiner’s obviousness conclusion? This issue
turns on whether the Examiner’s proposed modification renders the prior art
unsatisfactory for its intended purpose.

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FINDINGS OF FACT
The record supports the following additional findings of fact (FF) by a
preponderance of the evidence:
Hartmann
7. In one embodiment, Hartmann’s on-chip network comprises buses
configured in a mesh of rings with centralized switching via a central
switchpoint 340. The central switchpoint is surrounded by modules 210A-
210H. Hartmann, col. 5, l. 44 − col. 6, l. 13; Fig. 3A. This on-chip network
with centralized switching is shown in Figure 3A reproduced below:

Hartmann’s Figure 3A Showing On-Chip Network With Centralized
Switching

8. Connecting each module to a communications pathway with a full-
duplex, general purpose communications port allows for various module
types to form a networked system on a single computer chip. Hartmann, col.
3, ll. 12-16.

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Raatikainen
9. Raatikainen discloses a frame synchronized ring (FSR)
communications network (e.g., data bus 100). Bus 100 comprises nodes
(e.g., 102 and 104) connected together with unidirectional point-to-point
links 114 comprising a parallel data bus 106 and control lines. Data bus 100
is shown in Figure 1 reproduced below:

Raatikainen’s Data Bus 100 in Figure 1

10. Communication networks and their operations can be described
according to the Open Systems Interconnection (OSI) model that includes
seven layers that perform a specific data communications task. These layers
include (1) an application layer; (2) a presentation layer; (3) a session layer;
(4) a transport layer; (5) a network layer; (6) a data link layer; and (7) a
physical interface layer. Raatikainen, col. 1, l. 13 − col. 2, l. 34.
11. Raatikainen pertains to media access control (MAC) for
communication networks performed in the OSI network and data link layers.
Raatikainen, col. 2, ll. 35-48.
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12. One particular type of communication network is the ring
network that uses a series of point-to-point cables (twisted pair or coaxial)
connected between consecutive stations. Such a ring can have a
circumference of 1000 meters. Raatikainen, col. 2, ll. 49-64.
13. Bus 100 is a multi-access network where access control (i.e.,
operations of the MAC protocol) is distributed between the nodes. Each
node contains the necessary control logic to monitor the by-passing traffic to
decide when to receive and transmit data. Raatikainen, col. 11, ll. 44-51;
Fig. 1.
14. Transmission of data and access to the bus are dictated by the
MAC protocol algorithm shown in Figure 4. Raatikainen, col. 12, ll. 1-8;
Fig. 4.
15. The FSR MAC protocol is distributed between the nodes, thus
eliminating the need for a separate centralized control unit. Raatikainen, col.
13, ll. 19-24.
16. Two or more nodes can be housed in a single hardware device
(i.e., a physical node). Raatikainen, col. 20, ll. 20-22.

Appellant’s Disclosure
17. Appellant’s Specification notes that processor 706 has similar
characteristics and functions as MAC processor implemented within an OSI
model. Spec. 17:24-25, 19:2.
18. “[T]he higher-level circuit 708 is similar to an application layer
implemented within the OSI model.” Spec. 17:26-27.

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PRINCIPLES OF LAW
In rejecting claims under 35 U.S.C. § 103, it is incumbent upon the
Examiner to establish a factual basis to support the legal conclusion of
obviousness. See In re Fine, 837 F.2d 1071, 1073 (Fed. Cir. 1988). In so
doing, the Examiner must make the factual determinations set forth in
Graham v. John Deere Co., 383 U.S. 1, 17 (1966) (noting that 35 U.S.C.
§ 103 leads to three basic factual inquiries: (1) the scope and content of the
prior art; (2) the differences between the prior art and the claims at issue;
and (3) the level of ordinary skill in the art). Furthermore, the Examiner’s
obviousness rejection must be based on
“some articulated reasoning with some rational underpinning to
support the legal conclusion of obviousness” . . . . [H]owever,
the analysis need not seek out precise teachings directed to the
specific subject matter of the challenged claim, for a court can
take account of the inferences and creative steps that a person
of ordinary skill in the art would employ.

KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 418 (2007) (quoting In re
Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)).
If the Examiner’s burden is met, the burden then shifts to the
Appellants to overcome the prima facie case with argument and/or evidence.
Obviousness is then determined on the basis of the evidence as a whole and
the relative persuasiveness of the arguments. See In re Oetiker, 977 F.2d
1443, 1445 (Fed. Cir. 1992).
If the Examiner’s proposed modification renders the prior art
unsatisfactory for its intended purpose, the Examiner has failed to make a
prima facie case of obviousness. See In re Gordon, 733 F.2d 900, 902 (Fed.
Cir. 1984).
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ANALYSIS
Claims 1 and 4-10
We find no error in the Examiner’s obviousness rejection of
independent claim 1. First, our previous discussion regarding Hartmann’s
disclosure of packets of data applies equally here and we incorporate that
discussion by reference. Second, we agree with the Examiner (Ans. 15) that
nothing in the claim precludes Hartmann’s on-chip network (see, e.g., FF 7)
as constituting a “distributed bus architecture.”
Third, we see no reason why ordinarily skilled artisans could not have
applied Raatikainen’s fundamental concept of using a ring-based
architecture to transmit data between nodes (FF 9) to Hartmann’s on-chip
network as the Examiner proposes (Ans. 16-18).
In Raatikainen, the nodes monitor the network traffic to decide
whether to send and receive data in accordance with a MAC protocol
algorithm. FF 13 and 14. Notably, distributing the MAC protocol between
the nodes eliminates the need for a separate centralized control unit. FF 15.
Based on this functionality, we see no reason why Raatikainen’s MAC
protocol layers could not correspond to the recited nodes’ lower-level
processor and higher-level circuit as the Examiner indicates (Ans. 4 and 16),
particularly since Raatikainen explains that MAC functionality is performed
in conjunction with OSI network and data link layers (FF 11). Raatikainen
further notes that the OSI model includes seven layers including (1) an
application layer, and (2) network and data link layers (FF 10)—layers that
the Examiner equates to the recited “higher-level circuit” and “lower level
processor,” respectively (Ans. 4). We find no error in this approach. That
Appellant’s own disclosure indicates that the processor can have similar
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characteristics and functions as MAC processor implemented within an OSI
model (FF 17), and that the higher-level circuit “is similar to an application
layer implemented within the OSI model” (FF 18) only bolsters this
conclusion.
Lastly, we are not persuaded that modifying Hartmann’s on-chip
network in light of Raatikainen’s teachings as the Examiner proposes would
render the prior art inoperative or unsuitable for its intended purpose. The
Examiner unambiguously states that Raatikainen was relied upon merely for
the limited teaching of a single ring bus architecture where each node
comprises a lower level processor and a higher-level circuit. Ans. 15.
We acknowledge, however, that one particular application of
Raatikainen’s arrangement involves a 1000-meter ring network that uses
point-to-point cabling (FF 12) as Appellant argues (App. Br. 15-16; Reply
Br. 8). Nevertheless, we see no reason why skilled artisans could not apply
the fundamental concept of a single ring of serially-connected buses to an
on-chip network in lieu of the centralized switching arrangement of
Hartmann (FF 7), particularly since both references pertain to transferring
data between nodes in a network via buses. There is simply no evidence on
the record before us proving that the Examiner’s proposed modification of
Hartmann’s on-chip network could not be done or would somehow render
Hartmann’s on-chip network unsuitable for its intended purpose. To the
contrary, the evidence before us suggests that such a modification could be
beneficial, particularly since distributing a MAC protocol between the nodes
in Raatikainen eliminates the need for a separate centralized control unit (FF
15)—the very type of component that routes data in the centralized
switching arrangement of Hartmann. See FF 7.
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In any event, even if we assume, without deciding, that Raatikainen’s
network configuration was limited to LAN and WAN applications as
Appellant argues, that fact alone is not dispositive. It is well settled that “if a
technique has been used to improve one device, and a person of ordinary
skill in the art would recognize that it would improve similar devices in the
same way, using the technique is obvious unless its actual application is
beyond his or her skill.” KSR, 550 U.S. at 417. As such, we see no reason
why skilled artisans could not have applied Raatikainen’s fundamental
concept based on a ring-based network configuration that transfers data
between nodes via a bus (see FF 9-15) to an on-chip network which likewise
utilizes a network configuration to transfer data between nodes via buses
(see FF 1-4, 7, and 8). Nor is there any evidence on this record that such a
modification would have been beyond an ordinary artisan’s requisite level of
skill. Accordingly, we find the Examiner’s reason to combine the teachings
of Hartmann and Raatikainen supported by articulated reasoning with some
rational underpinning to justify the Examiner’s obviousness conclusion.
For the foregoing reasons, Appellant has not persuaded us of error in
the Examiner’s obviousness rejection of independent claim 1. Therefore, we
will sustain the Examiner’s rejection of that claim, and dependent claims 4-
10 and 25-29 not separately argued.

Claims 11-23
Likewise, we will sustain the Examiner's obviousness rejection of
independent claims 11 and 15. Although Appellant argues these claims
separately from claim 1 (App. Br. 13-20; Reply Br. 10-17), Appellant
essentially reiterates the same arguments made with respect to claim 1. See
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id. We are therefore not persuaded that the Examiner erred in rejecting
independent claims 11 and 15 for the same reasons discussed above with
respect to claim 1. Therefore, we will sustain the Examiner’s rejection of
those claims, and dependent claims 12-14 and 16-23 not separately argued.

THE OBVIOUSNESS REJECTION OVER HARTMANN, RAATIKAINEN, AND
BENZIMRA

We will also sustain the Examiner’s obviousness rejection of claims 5
and 19 over Hartmann, Raatikainen, and Benzimra (Ans. 13-14). Appellant
presented no arguments pertaining to this rejection, let alone particularly
point out errors in the Examiner’s reasoning to persuasively rebut the
Examiner's prima facie case of obviousness. The rejection is therefore
sustained.

CONCLUSION
Appellant has not shown that the Examiner erred in rejecting (1) claim
24 under § 102, and (2) claims 1, 4-23, and 25-29 under § 103.

ORDER
The Examiner’s decision rejecting claims 1 and 4-29 is affirmed.

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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

pgc

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