Ex Parte Conroy et al

Patent Trial and Appeal Board

Aug 29, 2014

12057146 (P.T.A.B. Aug. 29, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/057,146 03/27/2008 DAVID G. CONROY APPL:0017/MAN /
P5681US1
1806
65201 7590 08/29/2014
GAZDZINSKI & ASSOCIATES, P.C.
16644 WEST BERNARDO DRIVE
SUITE 201
SAN DIEGO, CA 92127
EXAMINER
BARTELS, CHRISTOPHER A.
ART UNIT PAPER NUMBER
2184
MAIL DATE DELIVERY MODE
08/29/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte DAVID G. CONROY, TIMOTHY J. MILLET, and
JOSEPH P. BRATT

___________

Appeal 2012-002655
Application 12/057,146
Technology Center 2100
____________

Before JOSEPH F. RUGGIERO, JOSEPH L. DIXON, and
ERIC B. CHEN, Administrative Patent Judges.

CHEN, Administrative Patent Judge.

DECISION ON APPEAL
This is an appeal under 35 U.S.C. § 134(a) from the final rejection of
claims 1–24, all the claims pending in the application. We have jurisdiction
under 35 U.S.C. § 6(b). We reverse.

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STATEMENT OF THE CASE
Appellants’ invention relates to accessing I/O and memory devices
utilizing a direct memory access DMA controller. Each device is connected
to the DMA controller through an individual channel. Clocking circuitry in
the DMA allows the DMA controller to send signals to each device at a
prescribed frequency. The DMA controller is capable of activating and
deactivating a channel clock, used in sending signals to the devices, based
on the operational status of the individual devices. The DMA controller is
also capable of tuning the channel clock dependent on the capabilities of any
active devices. (Abstract.)
Claims 1, 13, and 17 are exemplary, with disputed limitations in
italics:
1. A direct memory access (DMA) controller, comprising:
a control circuit adapted to receive device control information
and to generate clock control signals based on the device control
information;
a clock manager adapted to receive the clock control signals
and to activate and tune a plurality of DMA channel clock signals
based on the clock control signals; and
a plurality of DMA channel interface circuits adapted to receive
DMA command signals from the control circuit and one of the
plurality of tuned DMA channel clock signals from the clock
manager.

13. An electronic device, comprising:
a display adapted to display program icons;
a user interface adapted to interact with the display program
icons;
a central processing unit adapted to run programs associated
with the display program icons; and
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a DMA controller adapted to transmit and receive DMA
transfer signals to and from target and requesting devices, wherein the
DMA transfer signals include tuned DMA channel clock signals.

17. A method of accessing data, comprising:
receiving a DMA transfer request from a requesting device at a
DMA controller;
scheduling a DMA transfer based on the DMA transfer request;
transmitting clock control signals to a clock manager;
tuning a DMA channel clock in the clock manager based on the
clock control signals; and
transmitting DMA transfer signals from the DMA controller to
a target device, wherein the DMA transfer signals include a tuned
DMA channel clock.

Claims 1, 2, and 5–7 stand rejected under 35 U.S.C. § 102(b) as
anticipated by Fung (US 2006/0259796 A1; pub. Nov. 16, 2006).
Claims 17–20 and 22–24 stand rejected under 35 U.S.C. § 102(b) as
anticipated by Wilson (US 5,960,213; iss. Sept. 28, 1999).
Claims 3 and 4 stand reject under 35 U.S.C. § 103(a) as obvious over
Fung and Zaidi (US 7,062,587 B2; iss. June 13, 2006).
Claim 8 stands rejected under 35 U.S.C. § 103(a) as obvious over
Fung and Cruz (US 6,396,316 B1; iss. May 28, 2002).
Claims 9 and 10 stand reject under 35 U.S.C. § 103(a) as obvious over
Fung and Sihlbom (US 7,007,111 B2; iss. Feb. 28, 2006).
Claim 11 stands reject under 35 U.S.C. § 103(a) as obvious over Fung
and Normoyle (US 5,884,100; iss. Mar. 16, 1999).
Claim 12 stands reject under 35 U.S.C. § 103(a) as obvious over Fung
and Wang (US 2002/0062415 A1; pub. May 23, 2002).
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Claims 13–15 stand reject under 35 U.S.C. § 103(a) as obvious over
deCarmo (US 6,181,339 B1; iss. Jan. 30, 2001) and Fung.
Claim 16 stands reject under 35 U.S.C. § 103(a) as obvious over
deCarmo, Fung, and Wang.
Claim 21 stands reject under 35 U.S.C. § 103(a) as obvious over
Wilson and Wang.

ANALYSIS
§ 102 Rejection — Fung
We are persuaded by Appellants’ arguments (App. Br. 9) that Fung
does not describe the limitation “a control circuit adapted . . . to generate
clock control signals based on the device control information,” as recited in
independent claim 1.
The Examiner found that Fung discloses the limitation “a control
circuit adapted . . . to generate clock control signals based on the device
control information.” (Ans. 5, 34–35.) In particular, the Examiner found
that the power management unit (PMU), the South Bridge unit 223, and the
micro-controller 250 of Fung collectively correspond to the claimed “control
circuit.” (Id.) The Examiner further found that the System Flash ROM 237
and CMS of Fung corresponds to the claimed “device control information.”
(Id. at 6.) We do not agree.
Fung relates to “power consumption management and control systems
for high-density multi-server architectures.” (¶ 2.) Figure 11 of Fung
illustrates a functional block diagram of a server module 102 (¶ 109) that
includes a power management unit (PMU) 224, which is part of a South
Bridge unit 223 (¶ 110) (i.e., the claimed “control circuit”). Fung explains
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that a “[c]lock generator unit 232 receives a clock control signal 229 from
the PMU 224 component of the South Bridge Unit 223” (i.e., the claimed
“clock control signals”). (¶ 112.) Fung further explains that a System Flash
ROM 237 (i.e., the claimed “device control information”), which can be
used for storage of a Basic Input/Output System (BIOS), is coupled to the
South Bridge Unit 223 via a bus 238. (¶ 119.)
Claim 1 recites “a control circuit adapted . . . to generate clock control
signals based on the device control information” (emphasis added).
Although the Examiner cited the System Flash ROM 237 of Fung that stores
a Basic Input/Output System (BIOS) (¶ 119) that is IBM compatible (¶ 186),
the Examiner has provided insufficient evidence to support a finding that
Fung describes the limitation “to generate clock control signals based on the
device control information.” In particular, the Examiner has provided
insufficient evidence to demonstrate that the System Flash ROM 237 of
Fung (i.e., the claimed “device control information”) is used “to generate
clock control signals,” as recited in claim 1.
Accordingly, we are persuaded by Appellants’ argument that “there
does not appear to be a disclosure of utilizing any information read from
ROM 237 of FIG. 11 of Fung to ‘generate clock signals,’ as recited in
independent claim 1” and “Fung . . . appears to disclose clock generating
circuitry 232 . . . that appears to be wholly distinct from the disclosed system
flash ROM 237.” (App. Br. 9.)
Therefore, we do not agree with the Examiner that Fung describes the
limitation “a control circuit adapted . . . to generate clock control signals
based on the device control information.”
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Accordingly, we do not sustain the rejection of independent claim 1
under 35 U.S.C. § 102(b). Claims 2 and 5–7 depend from independent
claim 1. We do not sustain the rejection of claims 2 and 5–7 under 35
U.S.C. § 102(b) for the same reasons discussed with respect to independent
claim 1.

§ 102 Rejection — Wilson
We are persuaded by Appellants’ arguments (App. Br. 11; see also
Reply Br. 4–5) that Fung does not describe the limitation “tuning a DMA
channel clock,” as recited in independent claim 17.
The Examiner found that Wilson discloses the limitation “tuning a
DMA channel clock in the clock manager based on the clock control
signals.” (Ans. 10–11.) In particular, the Examiner found that the Latency
Timer of Wilson for managing PCI bus master corresponds to the limitation
“tuning a DMA channel clock in the clock manager.” (Id. at 10–11, 35.)
We do not agree.
Wilson relates to Peripheral Component Interconnect (PCI) bus
architectures. (Col. 1, l. 13.) Figure 3 of Wilson illustrates a multifunction
adapter that includes a Primary PCI Bus and a Secondary PCI Bus. (Col. 5,
ll. 9–13.) Wilson explains that a latency timer “specifies, in PCI bus clocks,
the value of the Latency Timer for this PCI bus master.” (Col. 13, ll. 34–
35.)
Although the Examiner cited the Latency Timer of Wilson (col. 13,
ll. 34–35), the Examiner has provided insufficient evidence to support a
finding that Wilson teaches the limitation “tuning a DMA channel clock in
the clock manager.” Furthermore, the Examiner has not provided a citation
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in Wilson for describing the limitation “based on the clock control signals.”
Accordingly, we are persuaded by Appellants’ argument that “nowhere in
Wilson is a discussion of ‘tuning a DMA channel clock’ and transmitting
‘DMA transfer signals’ wherein the DMA transfer signals include a ‘tuned
DMA channel clock . . . .’” (App. Br. 11; see also Reply Br. 4–5.)
Therefore, we do not agree with the Examiner that Wilson describes
the limitation “tuning a DMA channel clock.”
Accordingly, we do not sustain the rejection of independent claim 17
under 35 U.S.C. § 102(b). Claims 18–20 depend from independent
claim 17. We do not sustain the rejection of claims 18–20 under 35 U.S.C.
§ 102(b) for the same reasons discussed with respect to independent
claim 17.
Independent claim 22 recites limitations similar to those discussed
with respect to independent claim 17. We do not sustain the rejection of
claim 22, as well as dependent claims 23 and 24, for the same reasons
discussed with respect to claim 17.

§ 103 Rejection — Fung and Zaidi
Claims 3 and 4 depend from independent claim 1. Zaidi was cited by
the Examiner for teaching the additional features of claim 8. (Ans. 15–16.)
However, the Examiner’s application of Zaidi does not cure the above noted
deficiencies of Fung.

§ 103 Rejection — Fung and Cruz
Claim 8 depends from independent claim 1. Cruz was cited by the
Examiner for teaching the additional features of claim 8. (Ans. 18–19.)
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However, the Examiner’s application of Cruz does not cure the above noted
deficiencies of Fung.

§ 103 Rejection — Fung and Sihlbom
Claims 9 and 10 depend from independent claim 1. Sihlbom was
cited by the Examiner for teaching the additional features of claims 9 and
10. (Ans. 19–20.) However, the Examiner’s application of Sihlbom does
not cure the above noted deficiencies of Fung.

§ 103 Rejection — Fung and Normoyle
Claim 11 depends from independent claim 1. Normoyle was cited by
the Examiner for teaching the additional features of claim 11. (Ans. 21–22.)
However, the Examiner’s application of Normoyle does not cure the above
noted deficiencies of Fung.

§ 103 Rejection — Fung and Wang
Claim 12 depends from independent claim 1. Wang was cited by the
Examiner for teaching the additional features of claim 12. (Ans. 22–24.)
However, the Examiner’s application of Wang does not cure the above noted
deficiencies of Fung.

§ 103 Rejection — deCarmo and Fung
We are persuaded by Appellants’ arguments (App. Br. 19; see also
Reply Br. 6–7) that the combination of deCarmo and Fung would not have
rendered obvious independent claim 13, which includes the limitation
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“wherein the DMA transfer signals include tuned DMA channel clock
signals.”
The Examiner found that Fung teaches the limitation “wherein the
DMA transfer signals include tuned DMA channel clock signals.” (Ans. 26;
see also id. at 6.) In particular, the Examiner found that the first PCI clock
signal, the second PCI clock signal, and the third PCI clock signal of Fung
correspond to the limitation “tuned DMA channel clock signals.” (Id.) We
do not agree.
Appellants’ Specification discloses that “[t]he DMA controller may be
used to transfer data in an electronic device without burdening the central
processing unit (‘CPU’).” (Spec. ¶ 3.) In the context of computing, one
relevant plain meaning of “direct memory access” is “[m]emory access that
does not involve the microprocessor and is frequently used for data transfer
directly between memory and an ‘intelligent’ peripheral device, such as a
disk drive.” MICROSOFT® COMPUTER DICTIONARY 261 (5th ed. 2002).
Fung explains that “CPU 201 is coupled to a memory 208 . . . via
bus 210” and that “[a]dditional or expansion RAM 221 may optionally be
provided and is coupled to the CPU via bus 214.” (¶ 111.) Although the
Examiner cited to the server module of Fung, the Examiner has provided
insufficient evidence to support a finding the Fung teaches a “direct memory
access” or DMA as claimed, much less the limitation “wherein the DMA
transfer signals include tuned DMA channel clock signals.” Accordingly,
we are persuaded by Appellants’ argument that “Fung illustrates in FIG. 11
that a central processing unit (CPU) 201 has direct access to memory 208
(via path 210) and has direct access to memory 221 (via path 214) and that
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this CPU 201 is connected to the southbridge logic core 223 via a PCI bus.”
(App. Br. 19; see also Reply Br. 6–7.)
Thus, we do not agree with the Examiner that the combination of
deCarmo and Fung would have rendered obvious independent claim 13,
which includes the limitation “wherein the DMA transfer signals include
tuned DMA channel clock signals.”
Accordingly, we do not sustain the rejection of independent claim 13
under 35 U.S.C. § 103(a). Claims 14 and 15 depend from independent
claim 13. We do not sustain the rejection of claims 14 and 15 under 35
U.S.C. § 103(a) for the same reasons discussed with respect to independent
claim 13.

§ 103 Rejection — deCarmo, Fung, and Wang
Claim 16 depends from independent claim 13. Wang was cited by the
Examiner for teaching the additional features of claim 16. (Ans. 29–31.)
However, the Examiner’s application of Wang does not cure the above noted
deficiencies of deCarmo and Fung.

§ 103 Rejection — Wilson and Wang
Claim 21 depends from independent claim 17. Wang was cited by the
Examiner for teaching the additional features of claim 21. (Ans. 31–32.)
However, the Examiner’s application of Wang does not cure the above noted
deficiencies of Fung.

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DECISION
The Examiner’s decision rejecting claims 1–24 is reversed.

REVERSED

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