Ex Parte Cole et al

Patent Trial and Appeal Board

Oct 19, 2012

11054220 (P.T.A.B. Oct. 19, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte TERRY LYNN COLE, JAMES NICHOLS,
WILLIAM MICHAEL JOHNSON, and HARISH KUTAGULLA
____________

Appeal 2010-006140
Application 11/054,220
Technology Center 2100
____________

Before JOHN A. JEFFERY, BRUCE R. WINSOR, and JAMES B. ARPIN,
Administrative Patent Judges.

ARPIN, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1, 4-7, 12, 13, 22-30, 33-36, 43, and 47-50. We have
jurisdiction under 35 U.S.C. § 6(b). We affirm.

STATEMENT OF THE CASE
Appellants’ invention includes data processors that include a
processor core, an interface coupled to the processor core, and a
coprocessor. The coprocessor is coupled to the processor core via the
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interface and includes a first list memory. In response to a predetermined
instruction, the processor core provides an operand to the coprocessor via
the interface. The coprocessor stores the operand in the first list memory
and performs an operation corresponding to the predetermined instruction
using plural values from the first list memory to provide a result. See
generally Spec. ¶¶ [0009]-[0012]. Further, the invention includes methods
for performing data processing on a processor core, such as a central
processing unit, and a coprocessor and for transferring instructions and
operands between the processors. Spec. ¶ [0013].
Independent claim 1 is representative and is reproduced below with
the disputed claim term emphasized:
1. A data processor comprising:
a processor core;
an interface coupled to said processor core; and
a coprocessor coupled to said processor core via said interface, said
coprocessor including a first list memory,
wherein in response to a predetermined instruction said processor
core provides an operand to said coprocessor via said interface,
wherein said coprocessor stores said operand in said first list memory
and performs an operation corresponding to said predetermined
instruction using a plurality of values from said first list memory to
provide a result.

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THE REJECTION
The Examiner rejected claims 1, 4-7, 12, 13, 22-30, 33-36, 43, and 47-
501 under 35 U.S.C. § 103(a) as rendered obvious by Hinds (US 6,189,094
B1; issued Feb. 13, 2001) and Tanenbaum (Andrew S. Tanenbaum,
STRUCTURED COMPUTER ORGANIZATION 11-12 (2d ed. 1984)). Ans. 3-11.2

THE OBVIOUSNESS REJECTION OVER HINDS AND TANENBAUM
The Examiner finds that Hinds discloses every recited feature of
representative claim 1, except that Appellants have combined the loading of
the coefficient and signal values with the execution of the vector operation
on those values. Ans. 3-5. The Examiner, however, contends that
Tanenbaum teaches that hardware and software are logically equivalent and
that the choice between hardware and software is based on known factors.
Ans. 5. Thus, the Examiner concludes that combining the loading and
execution functions into a single instruction would have been an obvious
design choice. Ans. 5-6.
Appellants argue that the Examiner fails to establish a prima facie
case for obviousness for two reasons. App. Br. 5-7. First, Appellants argue
that the Examiner fails to demonstrate that Hinds and Tanenbaum
collectively disclose or suggest all of the limitations of the claimed
invention. App. Br. 7-10. In particular, Appellants argue that the applied

1 Claims 2, 3, 8-11, 14-21, 31, 32, 37-42, and 44-46 are withdrawn from
consideration as directed to unelected species of the invention. We note that
claim 50 is dependent from withdrawn claim 44.
2 Throughout this decision, we refer to (1) the Appeal Brief filed March 27,
2009 (supplemented September 1, 2009, and February 18, 2010), and (2) the
Examiner’s Answer mailed December 1, 2009.
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references fail to disclose or suggest “transferring an operand and
performing an operation on that operand and a plurality of other operands at
a coprocessor in response to a single instruction, as provided by the
independent claims.” Id. (bolding in original). Second, Appellants argue
that the Examiner fails to identify a reason to combine the applied references
to achieve the claimed invention. Id. Appellants also contend that Hinds
teaches away from its modification to combine multiple instructions into a
single instruction, as proposed by the Examiner. App. Br. 10.

ISSUES
(1) Under § 103, has the Examiner erred in rejecting claim 1 by
finding that Hinds and Tanenbaum would have disclosed or suggested “a
predetermined instruction,” giving that term its broadest reasonable
interpretation in light of the Specification?
(2) Is the Examiner’s reason to combine the teachings of Hinds and
Tanenbaum supported by articulated reasoning with some rational
underpinning to justify the Examiner’s obviousness conclusion?
(3) Does Hinds teach away from the modification proposed by the
Examiner in the obviousness rejection?

ANALYSIS
1. Claim Construction.
By their arguments, Appellants seek to distinguish independent claim
1 over the applied references by limiting “a predetermined instruction” to a
“single instruction.” App. Br. 8; see also App. Br. 12 (independent claim
13), 13 (independent claim 24), 15 (independent claim 30), 17 (independent
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claim 43). Consequently, we begin by construing the disputed term of claim
1 which recites, in pertinent part, “wherein in response to a predetermined
instruction said processor core provides an operand to said coprocessor via
said interface” (emphasis added).
In construing the meaning of the disputed claim term, we first
determine the ordinary and customary meaning of the term. Phillips v. AWH
Corp., 415 F.3d 1303, 1312-13 (Fed. Cir. 2005) (en banc). “[T]he ordinary
and customary meaning of a claim term is the meaning that the term would
have to a person of ordinary skill in the art in question at the time of the
invention, i.e., as of the effective filing date of the patent application.” Id. at
1313. This, however, is only the starting point of claim construction. We
must consider the claim term in the context of the written description of the
invention provided by the specification and the prosecution history. Id.
An instruction is “[a] pattern of digits which signifies to a computer
that a particular operation is to be performed and which may also indicate
the operands3 (or the locations of the operands) to be operated on.”
MCGRAW-HILL DICTIONARY OF SCIENTIFIC AND TECHNICAL TERMS 970 (4th
ed. 1989). A predetermined instruction is simply an instruction that has
been determined in advance. See OXFORD AMERICAN DICTIONARY 702
(Heald Colleges Ed. 1980) (definition of “to predetermine”). Nevertheless,
when an indefinite article, such as “a,” is used with a term in an open-ended
claim containing the transitional phrase “comprising,” the article may be
construed to mean “one or more.” Harari v. Lee, 656 F.3d 1331, 1341 (Fed.

3 An operand is “[a]ny one of the quantities entering into or arising from an
operation.” MCGRAW-HILL DICTIONARY OF SCIENTIFIC AND TECHNICAL
TERMS 1322 (4th ed. 1989).
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Cir. 2011). Thus, we initially construe the term “a predetermined
instruction” to mean one or more predetermined instructions.
Nevertheless, the Federal Circuit explains that, “[w]hen the claim
language and specification indicate that ‘a’ means one and only one, it is
appropriate to construe it as such even in the context of an open-ended
‘comprising’ claim.” Id. Consequently, we review the remainder of claim 1
and the other pending claims and the Specification to determine whether our
initial construction of this term is consistent. First, we note that, unlike in
Harari, Appellants’ use of the term in the first wherein clause of claim 1
does not suggest that the indefinite article was intended to specify a single
predetermined instruction. Although Appellants describe performing “an
operation corresponding to said predetermined instruction using a plurality
of values from said first list memory to provide a result” in the second
wherein clause of claim 1 (emphasis added), this language is consistent with
the definition of an “instruction,” as provided above, in which an instruction
is defined as signifying an operation to be performed on “operands.” Thus,
we do not find that Appellants’ use of the phase “a plurality of,” i.e., two or
more, elsewhere in the claim limits the meaning of the indefinite article “a”
to “one.” Moreover, referring to Figure 2, Appellants describe that “[a] set
of thirty-two signal lines 212 labeled ‘INSRUCTION’ [sic] corresponds to
one or more instructions in the instruction set of RISC processor core [300].”
Spec. ¶ [0024]. Consequently, we find that construing the disputed term to
mean “one or more predetermined instructions” is consistent with the use of
that term in claim 1 and in the context of the Specification.
As noted above, Appellants also argue that “claim 24 provides for
receiving an operand and performing an operation on that operand and a
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plurality of other operands at the coprocessor in response to a single
instruction,” i.e, a first predetermined instruction. App. Br. 13 (bolding in
original). In claim 25, which depends from claim 24, Appellants further
describe that “said first predetermined instruction comprises a finite impulse
response (FIR) filter start instruction” (emphasis added). Because claim
terms normally are used consistently throughout the patent, the usage of a
term in one claim often illuminates the meaning of the same term in other
claims. See Rexnord Corp. v. Laitram Corp., 274 F.3d 1336, 1342 (Fed. Cir.
2001). Thus, we strive to construe the term “a first predetermined
instruction” consistently between base claim 24 and dependent claim 25.
In addition, “[t]he doctrine of claim differentiation create[s] a
presumption that each claim in a patent has a different scope. The difference
in meaning and scope between claims is presumed to be significant [t]o the
extent that the absence of such difference in meaning and scope would make
a claim superfluous.” Free Motion Fitness, Inc. v. Cybex Int’l, Inc., 423
F.3d 1343, 1351 (Fed. Cir. 2005) (citations omitted) (internal quotation
marks omitted) (brackets in original). Thus, we find that Appellants
describe a specific example of a “first predetermined instruction” comprising
at least one particular instruction in claim 25. Because Appellants use the
open-ended, transitional phrase “comprising,” we find that, at least with
respect to claim 24, a “first predetermined instruction” is not strictly limited
to a single instruction. More generally, we find that construing the indefinite
article “a” to mean “one or more” in the disputed term in claim 1 is
consistent (a) with the appearance of the identical term in claims 13, 30, and
43 and (b) with the application of the doctrine of claim differentiation to
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claims 24 and 25. Therefore, we construe the term “a predetermined
instruction” to mean one or more predetermined instructions.
2. Hinds’s Disclosure of Predetermined Instruction.
Although the Examiner does not set forth an express construction of
the disputed claim term, the Examiner appears to accept Appellants’
argument that “a predetermined instruction” describes “a single instruction.”
Ans. 12. Nevertheless, claim construction is a question of law, and we
review the Examiner’s interpretation of the claim de novo. See In re
Donaldson Co., Inc., 16 F.3d 1189, 1192 (Fed. Cir. 1994). Thus, we apply
our construction of the disputed claim term when analyzing Appellants’
arguments.
“It is well established that the objective evidence of nonobviousness
must be commensurate in scope with the claims.” In re Lindner, 457 F.2d
506, 508 (CCPA 1972). Because we construe the term “a predetermined
instruction” to mean one or more predetermined instructions, we find that
Appellants’ arguments that “a predetermined instruction” is limited to “a
single instruction” are not commensurate in scope with the claim language.
Therefore, Appellants’ arguments do not demonstrate error in the
Examiner’s obviousness rejection of independent claim 1.
3. Adequacy of Reasons to Modify Hinds.
Appellants argue that the Examiner fails to establish that one skilled
in the relevant art would have a reason to combine the teachings of Hinds
and Tanenbaum, as proposed. App. Br. 7. As noted above, the Examiner
acknowledges that Hinds does not disclose or suggest combining “the
loading of the coefficient and signal values with the execution of the vector
operation on those values.” Ans. 5. The Examiner notes that “[Appellants]
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have taught no new circuitry or fabrication technology which makes their
instruction possible. They merely teach a design choice which depends on
the skill of one of ordinary skill to implement . . . .” Ans. 6. According to
Tanenbaum, hardware and software are logically equivalent, and any
operation that may be done in one also may be done in the other. Ans. 5.
More to the point, Tanenbaum states that “[t]he decision to put certain
functions in hardware and others in software is based on such factors as cost,
speed, reliability, and frequency of expected changes.” Ans. 5 (quoting
Tanenbaum, supra, at 11). Given the factors influencing design choices
described in Tanenbaum, the Examiner finds that one skilled in the relevant
art would have reason to combine the teachings of Hinds and Tanenbaum to
achieve Appellants’ distribution of operations between a core processor and
a coprocessor, as described in claim 1. Ans. 6. In particular, we find that
Appellants’ design choices predictably achieve reduced instruction storage
requirements and reduced energy consumption for memory and that these
encompass the same factors influencing design choices described by
Tanenbaum. See Ans. 6.
For the reasons set forth above, we construe Appellants’ claim 1 as
including, but not limited to, a single instruction. Therefore, we find that the
Examiner’s reason to combine the teachings of Hinds and Tanenbaum is
supported by articulated reasoning with some rational underpinning
sufficient to justify the Examiner’s obviousness conclusion.
4. Teaching Away from the Proposed Modification.
As noted above, Appellants contend that Hinds teaches away from its
modification to combine multiple instructions into a single instruction, as
proposed by the Examiner. App. Br. 10. A reference teaches away when a
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person of ordinary skill, upon reading the reference, would be discouraged
from following the path set out in the reference, or would be led in a
direction divergent from the path that was taken by Appellants. In re
Gurley, 27 F.3d 551, 553 (Fed. Cir. 1994). Appellants argue that Hinds’s
loading instruction, as depicted in Illustration 5, and Hinds’s execution
instruction, as depicted in Illustration 8, are 32 bits and 26 bits, respectively,
in length. App. Br. 10. Consequently, Appellants argue that the
combination of these two instructions would exceed the 32-bit size of
Hinds’s processor’s register. Id.
The Examiner identifies three flaws in Appellants’ argument. Ans.
13-15. First, the Examiner contends that the combination of the concepts of
the instructions is taught by the references, rather that the bodily
combination of the two particular instructions depicted in Hinds. Id.
Second, the Examiner contends that the size of a combined instruction does
not necessarily equal the depicted lengths of Hinds’s MCR and CDP
instructions. See id.; see also Hinds, col. 24, ll. 16-22; col. 30, ll. 29-39. By
eliminating redundancies and optimizing design, the length of the combined
instruction could be reduced. Ans. 14. Third, the Examiner notes that
Appellants do not describe a 32-bit instruction in claim 1, and do not assert
that their invention is implemented on Hinds’s hardware. Id. We find the
Examiner’s response to Appellants’ arguments persuasive. In addition, we
note that Hinds describes that the registers of resister bank 38 of coprocessor
26 “can operate individually as single precision registers each storing a 32-
bit data value or as pairs that together store a 64-bit data value.” Hinds,
col. 4, ll. 62-65 (emphasis added); see also col. 11, ll. 35-54.
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For the reasons set forth above, however, we find that Appellants’
claim 1 is not limited to a single instruction. Therefore, even if Hinds taught
away from combining multiple instructions into a single instruction, this
would not teach away from the modification of Hinds to achieve the
invention, as described in Appellants’ claim 1.
On this record, we find that Appellants fail to demonstrate error in the
Examiner’s obviousness rejection of representative claim 1. Therefore, we
sustain the Examiner’s obviousness rejection of independent claim 1, as well
as claims 4-7, 12, 13, 22-30, 33-36, 43, and 47-50, of which claim 1 is
representative.4

CONCLUSION
The Examiner did not err in rejecting claims 1, 4-7, 12, 13, 22-30, 33-
36, 43, and 47-50 under § 103(a).

ORDER
The Examiner’s decision rejecting claims 1, 4-7, 12, 13, 22-30, 33-36,
43, and 47-50 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

4 Although we identify “a predetermined instruction” as the disputed claim
term and review the obviousness rejection in view of our construction of that
term, this should not be interpreted as a finding that claim 1 or any of the
pending claims satisfies the requirements of 35 U.S.C. § 112, ¶ 2. If
prosecution of this application is reopened, the Examiner should consider
whether claims 1, 4-7, 12, 13, 22-30, and 33-36 satisfy the requirements of
35 U.S.C. § 112, ¶ 2. See MPEP § 2173.05(p)(II).
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AFFIRMED

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