Ex Parte Claydon

Patent Trial and Appeal Board

Oct 25, 2012

10450615 (P.T.A.B. Oct. 25, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/450,615 11/21/2003 Anthony Peter John Claydon 055328/411437 4318
53388 7590 10/25/2012
WEIDE & MILLER - MINDSPEED
7251 WEST LAKE MEAD BLVD.
SUITE 530
LAS VEGAS, NV 89128
EXAMINER
COLEMAN, ERIC
ART UNIT PAPER NUMBER
2183
MAIL DATE DELIVERY MODE
10/25/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte ANTHONY PETER JOHN CLAYDON
____________

Appeal 2010-005172
Application 10/450,615
Technology Center 2100
____________

Before JEFFREY S. SMITH, ERIC B. CHEN, and JEREMY J. CURCURI,
Administrative Patent Judges.

SMITH, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2010-005172
Application 10/450,615

2
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from claims 1-26, 28, and
29. Claims 27 and 30 have been canceled. We have jurisdiction under
35 U.S.C. § 6(b).
We reverse.

Illustrative Claim
1. A processor architecture comprising:

a plurality of processing elements, each element having at least one
input port and at least one output port, each port having at least a data bus
and a valid data signal line;

and a bus structure which contains a plurality of switches which are
arranged so as to allow an output port of any first processing element to be
connected to the input port of any second processing element for a time
interval;

each processing element being enabled to set a value on the valid data
signal line of its output port to a first logic state when the associated data bus
contains a transfer value, and to a second logic state when the data bus does
not contain a transfer value;

each processing element being further enabled to enter a low power
sleep mode for a predetermined time interval when the value on the valid
data signal line of the associated input port is in the second logic state.

Prior Art
Mason US 5,926,640 Jul. 20, 1999
Schmidt et al., Datawave: A Single-Chip Multiprocessor for video
Applications, IEEE Micro, IEEE Inc. vol. 11, No. 3, 22-25 and 88-94,
(1991).

Appeal 2010-005172
Application 10/450,615

3
Muhammad Ali Mazidi et al., The 80x86 IBM PC and Compatible
Computers, Prentice Hall, Inc., 4th ed. 513-515, (2003).

Examiner’s Rejections
Claims 1-17 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Schmidt.
Claims 18-26, 28, and 29 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Schmidt and Mason.

ANALYSIS
Section 102 rejection of claims 1-17
Claim 1 recites “a bus structure which contains a plurality of switches
which are arranged so as to allow an output port of any first processing
element to be connected to the input port of any second processing element
for a time interval.” The Examiner cites to Figure 1 of Schmidt to show a
plurality of processing elements, cites to Figure 3B of Schmidt to show a bus
structure to allow an output port of any processing element to connect to an
input port of any other processing element. Ans. 4. Appellant contends that
Figures 1 and 3B of Schmidt are showing different embodiments of
Schmidt’s device. App. Br. 6-7.
Figure 1 of Schmidt shows the architecture of each of the processors
shown in Figure 3B. The Examiner is citing to different embodiments
described by Schmidt, which does not establish anticipation of claim 1. See
Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008).
Further, neither Figure 1 nor Figure 3B show that any processing element
can connect to any other processing element. Both Figures show that a
Appeal 2010-005172
Application 10/450,615

4
processing element can only connect to one of (at most) four neighboring
processing elements.
We do not sustain the rejection of claim 1 and corresponding
dependent claims 2-16 under 35 U.S.C. § 102. Independent claim 17
contains a limitation similar to that of claim 1 for which the rejection fails.

Section 103 rejection of claims 18-26, 28, and 29
The Examiner has not established that the combination of Schmidt
and Mason teaches “a bus structure which contains … switches which are
located at intersections of the horizontal and vertical buses and arranged so
as to allow an output port of any first array element to be connected to the
input port of any second array element for a time interval” as recited in
independent claim 17. We do not sustain the rejection of dependent claims
18-26, 28, and 29 under 35 U.S.C. § 103.

DECISION
The rejection of claims 1-17 under 35 U.S.C. § 102(b) as being
anticipated by Schmidt is reversed.
The rejection of claims 18-26, 28, and 29 under 35 U.S.C. § 103(a) as
being unpatentable over Schmidt and Mason is reversed.

REVERSED

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