Ex Parte Chung et al

Patent Trial and Appeal Board

Oct 31, 2012

11470019 (P.T.A.B. Oct. 31, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/470,019 09/05/2006 Shine Chung 2003.1256CON/1280.430 7129
54657 7590 11/01/2012
DUANE MORRIS LLP (TSMC)
IP DEPARTMENT
30 SOUTH 17TH STREET
PHILADELPHIA, PA 19103-4196
EXAMINER
CHENG, DIANA
ART UNIT PAPER NUMBER
2816
MAIL DATE DELIVERY MODE
11/01/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE PATENT TRIAL AND APPEAL BOARD
___________
Ex parte SHINE CHUNG, KENNETH CHIAKUN WENG,
and PIN-LIN CHIU
___________
Appeal 2010-006489
Application 11/470,019
Technology Center 2800
__________

Before MARC S. HOFF, CARLA M. KRIVAK, and ELENI MANTIS
MERCADER, Administrative Patent Judges.
MANTIS MERCADER, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-006489
Application 11/470,019

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STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the final rejection of
claims 1, 2, 6, 12, 19, 20, 22, 23, and 28. Claims 3-5, 7-11, 13, 21, 24-27,
and 37 have been cancelled. Claims 14-18, 29-32, and 35 are withdrawn.
We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
THE INVENTION
Appellants’ claimed invention is directed to an edge triggered flip-
flop having a data storage circuit which temporarily stores a first storage
signal, (see generally Spec. ¶¶ [0008]-[0009]).
Independent claim 1, reproduced below, is representative of the
subject matter on appeal.
1. An edge triggered flip-flop circuit comprising:
a clock node for receiving a clock signal;
an input node for receiving an input signal;
a switch module using the clock signal for defining a data passing
window; and
a latch module for receiving the input signal during the data passing
window,
wherein the switch module includes a pair of pass gates coupled in
series between the input node and a data node of the latch module, the
switch module further including a temporary storage device coupled
to the pair of pass gates, a first one of the pass gates controlled by the
Appeal 2010-006489
Application 11/470,019

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clock signal and a second one of the pass gates controlled by an
inverted clock signal, wherein the first pass gate is turned on to store
the input signal to the temporary storage device and then the second
pass gate is turned on to pass the stored input signal to the latch
module, wherein the second pass gate shuts off at the end of the data
passing window.
REFERENCES and REJECTION
The Examiner rejected claims 1, 2, 6, 12, 28, 33, 34, and 36 are
rejected under 35 U.S.C. § 103(a) as being unpatentable over Nguyen (US
6,501,315 B1; filed Dec. 31, 2002), Park et al. (US 6,646,492 B2; filed Nov.
11, 2003), and Hashimoto et al. (US 5,198,699; filed Mar. 30, 1993).
ISSUE
The issue is whether the Examiner erred in finding that the
combination of Nguyen, Park, and Hashimoto teaches the limitation:
“wherein the first pass gate is turned on to store the input signal to the
temporary storage device and then the second pass gate is turned on to pass
the stored input signal to the latch module, wherein the second pass gate
shuts off at the end of the data passing window” as recited in claim 1.
PRINCIPLES OF LAW
If proposed modification would render the prior art invention being
modified unsatisfactory for its intended purpose, then there is no suggestion
or motivation to make the proposed modification. In re Gordon, 733 F.2d
900, 902 (Fed. Cir. 1984).

Appeal 2010-006489
Application 11/470,019

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ANALYSIS
Appellants argue that Park does not teach a temporary storage device
“wherein the first pass gate is turned on to store the input signal to the
temporary storage device and then the second pass gate is turned on to pass
the stored input signal to the latch module” (App. Br. 9). The Examiner
relies on Hashimoto for teaching incorporating a capacitor between two pass
gates connected in series for “insulating the transmission of data on the
transmission line from current spikes on the supply source” (Ans. 11).
We agree with Appellants that Park discloses a flip flop with a series
of pass gates (see in Fig. 11, pass gates 1121 and 1122) to pass data directly
to latch 1130 when both pass gates are “on” and the delayed inverted clock
signal overlaps the original clock signal to create a data passing window
(App. Br. 9; also see Park, col. 8, ll. 4-38, describing how the gates work).
The inclusion of a temporary storage device (i.e., a capacitor), as taught by
Hashimoto (see Fig. 1, element 28), would interfere with and destroy the
functionality of the pass gates to pass data directly to the storage latch of
Park, because the capacitor would store the signal and thereby interfere with
the data passing window. The proposed modification would render Park’s
prior art invention modified with Hashimoto’s capacitor unsatisfactory for
its intended purpose of creating a data passing window. Thus, there is no
suggestion or motivation to make the proposed modification. See In re
Gordon, 733 F.2d at 902.
Accordingly, we reverse the Examiner’s rejection of claim 1, and for
the same reasons the rejections of claims 2, 6, 12, 28, 33, 34, and 36 which
were not separately argued.
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CONCLUSION
The Examiner erred in finding that the combination of Nguyen, Park,
and Hashimoto teaches the limitation: “wherein the first pass gate is turned
on to store the input signal to the temporary storage device and then the
second pass gate is turned on to pass the stored input signal to the latch
module, wherein the second pass gate shuts off at the end of the data passing
window” as recited in claim 1.
DECISION
The Examiner’s decision rejecting claims 1, 2, 6, 12, 28, 33, 34, and
36 is reversed.
REVERSED
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