Ex Parte Cho et al

Patent Trial and Appeal Board

Feb 11, 2016

12164757 (P.T.A.B. Feb. 11, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/164,757 06/30/2008 In Sung Cho
120363 7590 02/16/2016
Lattice Semiconductor/FENWICK
801 California Street
Mountain View, CA 94041
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
30850-25683 1839
EXAMINER
MURPHY, CHARLES C
ART UNIT PAPER NUMBER
2455
NOTIFICATION DATE DELIVERY MODE
02/16/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ptoc@fenwick.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte IN SUNG CHO, KUMAR MARESH,
PRAKASH KAMATH, JEFFREY GILBERT, and
ROB FRIZZELL
Appeal2013-010358
Application 12/164,757 1
Technology Center 2400
Before DEBRA K. STEPHENS, KEVIN C. TROCK, and
JESSICA C. KAISER, Administrative Patent Judges.
Per Curiam.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134 from a Final Rejection of
claims 1-20. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
1 According to Appellants, the Real Party in Interest is SiBeam, Inc. Br. 3.
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Application 12/164,757
STATEMENT OF THE INVENTION
According to Appellants, the claims are directed to a method and
apparatus for exchanging information between a host processor and
transceiver using an I2C interface and multiple banks of memory. Abstract.
Claim 1, reproduced below, is illustrative of the claimed subject matter:
1. An apparatus for use in a wireless communication system
for communicating with a wireless network, the apparatus
compnsmg:
a host processor having an I2C interface;
a transceiver having an I2C interface;
a physical interface coupling the host processor and the
transceiver, the physical interface comprising an I2C bus coupled
to the I2C interface of both the host processor and the transceiver;
and
a plurality of separate banks of memory accessible by the
host processor and the transceiver to exchange information
between the host processor and the transceiver, including:
a first bank to store information being transferred
from the host processor to the transceiver;
a second bank to store information being transferred
from the transceiver to the host processor; and
a third bank to store control registers to control
interactions between the host processor and the
transceiver.
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Call way
Nouzovsky
Khandekar
US 2003/0027517 Al Feb. 6, 2003
US 6,819,677 Bl Nov. 16, 2004
US 2008/0062178 Al Mar. 13, 2008
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Application 12/164,757
Mac Mullan US 7,499,462 B2 Mar. 3, 2009
Philips Semiconductors, The !2C-Bus Specification Version 2.1 (January
2000) (hereinafter "I2C Specification").
REJECTIONS
Claims 1-3, 10-13, and 20 stand rejected under 35 U.S.C. §103(a) as
being unpatentable over MacMullan, Nouzovsky, and Callway. Final Act.
2-15.
Claims 4, 5, 14, and 15 stand rejected under 35 U.S.C. §103(a) as
being unpatentable over MacMullan, Nouzovsky, Callway, and Khandekar.
Final Act. 15-18.
Claims 6-9 and 16-19 stand rejected under 35 U.S.C. §103(a) as
being unpatentable over MacMullan, Nouzovsky, Callway, and I2C
Specification. Final Act. 18-26.
\Ve have considered only those arguments that 1A .. ppellants actually
raised in the Briefs. Arguments Appellants could have made but chose not
to make in the Briefs have not been considered and are deemed to be
waived. See 37 C.F.R. § 41.37(c)(l)(iv).
ISSUE
Did the Examiner err by finding the combination of MacMullan,
Nouzovsky, and Callway teaches or suggests "a third bank to store control
registers to control interactions between the host processor and the
transceiver," as recited in claims 1 and 11?
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ANALYSIS
We have reviewed the Examiner's rejections in light of Appellants'
arguments that the Examiner has erred. We disagree with Appellants'
conclusions. We adopt as our own the findings and reasons set forth by the
Examiner in the Final Action from which the appeal is taken (Final Act. 2-
26), the Advisory Action dated September 24, 2012 (Adv. Act. 2) and the
reasons set forth in the Examiner's Answer in response to Appellants'
Appeal Brief (Ans. 3---6). We highlight and address specific findings and
arguments for emphasis as follows.
Appellants argue Callway does not disclose "a third bank to store
control registers to control interactions between the host processor and the
transceiver," as recited in claims 1 and 11. Br. 7-12. Specifically,
Appellants argue Callway's drawing control registers do not "store
commands issued" between the CPU and transceiver, but instead "are
implemented to store a status." Br. 11 (citing Callway i-f 48). Appellants
also argue Callway's control register does not "control interactions between
a host processor and transceiver," but instead is used "to control a
multiplexing circuit." Br. 12 (citing Call way i-f 20) (emphasis omitted).
Appellants' arguments are not persuasive because the rejection is
based on obviousness. The Examiner relies on MacMullan for teaching a
host processor interacting with a transceiver by using an I2C interface to
transfer data packets and Callway for teaching a host processor that interacts
with other system components through commands issued by the CPU. Adv.
Act. 2 (citing Call way i-f 53 ("commands sent by the host CPU"), 56 ("writes
controlled by the host CPU")); Final Act. 3 (citing MacMullan 23:42---64);
see also MacMullan Fig. 22. The Examiner further finds, and we agree,
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Callway teaches commands that control system components can be provided
using control registers. Ans. 6 (citing Call way i-f 20 ("multiplexing circuit
140 is then controlled via a control register 142"), 56 (drawing control
registers are used to ensure the same data is processed by image renderers);
see also Adv. Act. 2. Based on Callway's teaching that a host processor
controls system components using commands and that commands can be
provided by control registers, the Examiner concludes, and we agree, that
one of ordinary skill in the art would have found it obvious to use Callway's
control registers to provide commands for controlling interactions between
the host processor and another system component-in this case, the
transceiver-to "improve the efficiency in transmitting wireless video data."
Final Act. 5-6; see also Ans. 6. Appellants' arguments, that drawing control
registers store statuses and multiplexer commands are not host processor
commands, do not persuade us that using Callway's control registers to
control interactions between known system components-here, a host
processor and a transceiver-would have been more than using a known
technique in a same way, that was not uniquely challenging or beyond the
skill of an ordinarily skilled artisan.
Additionally, Appellants' argument that the Examiner improperly
combines Callway's control registers and drawing control registers is
misplaced. Br. 12. The Examiner does not combine various control
registers; rather, as discussed supra, the Examiner relies on Callway's
control registers and drawing control registers to teach examples of using
control registers to control system components. Ans. 6.
Therefore, Appellants have not persuaded us the Examiner erred in
finding the combination ofMacMullan, Nouzovsky, and Callway teaches or
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at least suggests "a third bank to store control registers to control
interactions between the host processor and the transceiver," as recited in
independent claim 1 and commensurately recited claim 11. Accordingly, we
are not persuaded the Examiner erred in rejecting claims 1 and 11 under 35
U.S.C. § 103(a).
Dependent claims 2-10 and 12-20 were not separately argued, but
instead were argued as being patentable based on their dependence from
independent claims 1and11, respectively. Br. 7, 13. It follows, we sustain
the rejection of claims 2-10 and 12-20 under 35 U.S.C. § 103(a).
DECISION
The Examiner's rejection of claims 1-3, 10-13, and 20 under 35
U.S.C. §103(a) as being unpatentable over MacMullan, Nouzovsky, and
Callway is affirmed.
The Examiner's rejection of claims 4, 5, 14, and 15 under 35 U.S.C.
§103(a) as being unpatentable over MacMullan, Nouzovsky, Callway, and
Khandekar is affirmed.
The Examiner's rejection of claims 6-9 and 16-19 under 35 U.S.C.
§103(a) as being unpatentable over MacMullan, Nouzovsky, Callway, and
I2C Specification is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv) (2009).
AFFIRMED
dw
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