Ex Parte Chiu et al

Board of Patent Appeals and Interferences

Jul 30, 2010

11229188 (B.P.A.I. Jul. 30, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/229,188 09/15/2005 Robert J. Chiu 0180359D 2267
25700 7590 08/02/2010
FARJAMI & FARJAMI LLP
26522 LA ALAMEDA AVENUE, SUITE 360
MISSION VIEJO, CA 92691
EXAMINER
WRIGHT, TUCKER J
ART UNIT PAPER NUMBER
2891
MAIL DATE DELIVERY MODE
08/02/2010 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte ROBERT J.CHIU, PAUL R.BESSER, SIMON SIU-SING CHAN,
JEFFERY P. PATTON, AUSTIN C. FRENKEL,
THORSTEN KAMMLER, and ERROL TODD RYAN
____________________

Appeal 2009-011552
Application 11/229,1881
Technology Center 2800

____________________

Before MARC S. HOFF, CARLA M. KRIVAK,
and ELENI MANTIS MERCADER, Administrative Patent Judges.

HOFF, Administrative Patent Judge.

DECISION ON APPEAL2

1 The real party in interest is Global Foundries Inc.
2 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or filing a request for rehearing, as
recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE” (paper
delivery mode) or the “NOTIFICATION DATE” (electronic delivery mode)
shown on the PTOL-90A cover letter attached to this decision.

Appeal 2009-011552
Application 11/229,188

2
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134 from a Final Rejection of
claims 12, 13, 15-17, and 19. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
Appellants’ invention relates to an integrated circuit that includes “a
gate dielectric formed on a semiconductor substrate, and a gate formed over
the gate dielectric. A sidewall spacer is formed around the gate and a
source/drain junction is formed in the semiconductor substrate using the
sidewall spacer. A bottom silicide metal is deposited on the source/drain
junction and then a top silicide metal is deposited on the bottom silicide
metal. The bottom and top silicide metals are formed into their silicides. A
dielectric layer is deposited above the semiconductor substrate and a contact
is formed in the dielectric layer to the top.” (Figs. 1-8; Abstract).
Claim 12 is exemplary:
12 An integrated circuit comprising:
a semiconductor substrate;
a gate dielectric on the semiconductor substrate;
a gate over the gate dielectric;
a sidewall spacer around the gate;
a source/drain junction in the semiconductor substrate adjacent the
sidewall spacer;
a bottom silicide over the source/drain junction, the bottom silicide of
cobalt silicide using cobalt of a thickness under 10 Angstroms;
a top silicide over the bottom silicide, the top silicide of nickel silicide
using nickel of a thickness such that the cobalt silicide blocks diffusion of
the nickel silicide into the semiconductor substrate;
a dielectric layer above the semiconductor substrate; and
a contact in the dielectric layer to the top silicide.

Appeal 2009-011552
Application 11/229,188

3
The prior art relied upon by the Examiner in rejecting the claims on appeal
is:
Chung US 5,646,070 Jul. 8, 1997
Bertrand US 6,468,900 B1 Oct. 22, 2002
Sugimae US 2003/0151069 A1 Aug. 14, 2003
Yang US 6,806,157 B2 Oct. 19, 2004

Claims 12, 13, and 15 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Bertrand in view of Chung.
Claims 16, 17, and 19 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Bertrand in view of Chung, Yang, and Sugimae.
Rather than repeat the arguments of Appellants or the Examiner, we
make reference to the Appeal Brief (filed December 5, 2008) and the
Examiner’s Answer (mailed February 23, 2009) for their respective details.

ISSUE
Appellants contend that in Bertrand, during rapid thermal annealing
(RTA), the nickel atoms diffuse from nickel layer 204 across cobalt layer
202 and into doped silicon region 24 forming a mixed metal silicide region
206 over doped silicon 24 (Bertrand col. 5, l. 61-col. 6, l. 4). However,
claim 12 requires forming “a top silicide of nickel silicide over the bottom
silicide.” (App. Br. 7 and 9 (emphasis added)).
Appellants’ contentions present us with the following issue: Do the
references disclose an integrated circuit including a top silicide layer of
nickel silicide formed over a bottom silicide layer of cobalt silicide, wherein
the nickel silicide has a thickness such that the cobalt silicide blocks
diffusion of the nickel silicide into the semiconductor substrate?

Appeal 2009-011552
Application 11/229,188

4
FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
The Invention
1. According to Appellants, the invention relates to an integrated
circuit that includes a gate dielectric (104) is formed on a semiconductor
substrate (102) and a gate (106) formed over the gate dielectric (104). A
sidewall spacer (402) is formed around the gate (106) and a source/drain
junction (304 and 306) is formed in the semiconductor substrate (102) using
the sidewall spacer (402). A bottom silicide metal (604, 606, and 608) is
deposited on the source/drain junction (504) and then a top silicide metal
(704, 706, and 708) is deposited on the bottom silicide metal (604, 606, and
608). The bottom and top silicide metals are formed into their silicides (804,
806, 808, 814, 816, and 818). A dielectric layer (900) is deposited above the
semiconductor substrate (102) and a contact (902, 904, and 906) is formed in
the dielectric layer (900) to the top. (Figs 1-8; Abstract).
Bertrand
2. Bertrand discloses a semiconductor device 20 which is
subjected to deposition of a thin barrier layer 202 of non-nickel metal such
as cobalt (col. 5, ll 13-14). In one embodiment, a nickel metal layer 204 is
deposited over the cobalt metal layer 202 (col. 5, ll. 34-36). After deposition
of the nickel metal layer 204, the device 20 is subjected to a rapid thermal
annealing (RTA) (col. 5, ll. 60-61). “During the RTA step, nickel atoms
diffuse from the nickel layer 204 across the cobalt layer 202 and into the
doped silicon region 24, and gate electrode 26, where the nickel atoms react
with Si atoms to form nickel silicide (NiSi)” (col. 5, ll. 63-66).
Appeal 2009-011552
Application 11/229,188

5
Simultaneously, cobalt atoms diffuse from the cobalt layer 202 into the
doped silicon region 24, where the cobalt atoms react with the Si atoms to
form cobalt silicide (CoSi). The cobalt silicide and nickel silicide atoms
form mixed metal silicide region 206 over the doped silicon region 24 (col.
5, l. 67- col. 6, l. 4).
3. Bertrand discloses that when the semiconductor device is
subjected to RTA, nickel metal atoms diffuse across the cobalt metal layer
into the doped silicon region of the semiconductor device while cobalt atoms
simultaneously diffuse into the doped silicon region to respectively form
nickel silicide (NiSi) and cobalt silicide (CoSi). A slow moving dispersion
front of cobalt silicide molecules form as cobalt diffuses into the doped
silicon region during RTA. Ni metal atoms pile behind this slow moving
dispersion, forming the nickel silicide (col. 7, ll. 24-30).

PRINCIPLES OF LAW
On the issue of obviousness, the Supreme Court has stated that “the
obviousness analysis cannot be confined by a formalistic conception of the
words teaching, suggestion, and motivation.” KSR Int’l Co. v. Teleflex Inc.,
550 U.S. 398, 419 (2007). Further, the Court stated “[t]he combination of
familiar elements according to known methods is likely to be obvious when
it does no more than yield predictable results.” Id. at 416.
The question of obviousness is resolved on the basis of underlying
factual determinations including (1) the scope and content of the prior art,
(2) any differences between the claimed subject matter and the prior art, (3)
the level of skill in the art, and (4) where in evidence, so-called secondary
considerations. Graham v. John Deere Co., 383 U.S. 1, 17-18 (1966).
Appeal 2009-011552
Application 11/229,188

6
ANALYSIS
Claims 12, 13, and 15
Independent Claim 12 recites an integrated circuit that comprises “a
top silicide over [a] bottom silicide [of cobalt silicide], the top silicide of
nickel silicide using nickel of a thickness such that the cobalt silicide blocks
diffusion of the nickel silicide into the semiconductor substrate.”
We are persuaded by Appellants’ arguments (see Issue section,
supra). Although Bertrand discloses that the cobalt silicide molecules form
a slow moving dispersion front ahead of the nickel silicide molecules,
Bertrand discloses that the cobalt silicide and nickel silicide molecules mix
together to form a mixed metal silicide region 206 over the doped silicon
region 24 (FF 2 and 3 (emphasis added)).
In making an obviousness determination, the question of obviousness
is resolved on the basis of underlying factual determinations including the
scope and content of the prior art. Id. at 17-18. Bertrand does not disclose a
top silicide of nickel silicide over a bottom silicide of cobalt silicide. Rather,
Bertrand discloses a mixed metal silicide region 206 over the doped silicon
region 24 (FF 2). Thus, Bertrand discloses that cobalt and nickel silicides
mix and are not blocked from diffusing into each other, contrary to what is
claimed.
Therefore, we find that the Examiner has not established a prima facie
case of obviousness of the claims, because neither Bertrand nor Chung teach
an integrated circuit including a top silicide layer formed over a bottom
silicide layer of cobalt silicide. As a result, we will not sustain the
Examiner’s § 103 rejection of claims 12, 13, and 15.
Appeal 2009-011552
Application 11/229,188

7
Claims 16, 17, and 19
Independent claim 16 recites “a nickel silicide over the cobalt silicide,
the nickel silicide being formed form nickel of a thickness such that the
cobalt silicide blocks diffusion of the nickel silicide into the semiconductor
substrate.”
Appellants argue that independent claim 16 is patentable over the
cited prior art because the claim is similar in scope to independent claim 12
and because Yang does not cure the deficiencies asserted with respect to the
Bertrand and Chung references (App. Br. 13).
As noted supra, we find that Bertrand and Chung do not teach all the
features of claim 12. We have reviewed Yang, and find that it does not cure
the deficiencies deemed to be absent from Bertrand and Chung.
We therefore reverse the Examiner’s rejection of claims 16, 17, and
19 under 35 U.S.C. § 103, for the same reasons expressed with respect to
independent claim 12, supra.

CONCLUSION
The references do not disclose an integrated circuit including a top
silicide layer of nickel silicide formed over a bottom silicide layer of cobalt
silicide, wherein the nickel silicide has a thickness such that the cobalt
silicide blocks diffusion of the nickel silicide into the semiconductor
substrate.
ORDER
The Examiner’s rejection of claims 12, 13, 15-17, and 19 is reversed.

REVERSED
Appeal 2009-011552
Application 11/229,188

8

ELD

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