Ex Parte Chitlur

Patent Trial and Appeal Board

Feb 16, 2016

12217089 (P.T.A.B. Feb. 16, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/217,089 06/30/2008
104333 7590 02/18/2016
International IP Law Group, P,LLC
Lauren W. Burke
c/o CPA Global
P.O. Box 52050
Minneapolis, MN 55402
FIRST NAMED INVENTOR
Nagabhushan Chitlur
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
P27232 7587
EXAMINER
HUYNH,KIMT
ART UNIT PAPER NUMBER
2185
NOTIFICATION DATE DELIVERY MODE
02/18/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
eofficeaction@appcoll.com
Intel_Docketing@iiplg.com
inteldocs _ docketing@cpaglobal.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte NAGABHUSHAN CHITLUR
Appeal2014-002197
Application 12/217,089
Technology Center 2100
Before KAL YANK. DESHPANDE, DAVID M. KOHUT, and
JUSTIN T. ARBES, Administrative Patent Judges.
DESHPANDE, Administrative Patent Judge.
DECISION ON APPEAL
Appeal2014-002197
Application 12/217,089
STATEMENT OF CASE1
Appellant seeks review under 35 U.S.C. § 134(a) of the Examiner's
final rejection of claims 1-27. We have jurisdiction over the appeal
pursuant to 35 U.S.C. § 6(b).
We AFFIRM.
Appellant's invention is directed to memory mapping of control and
status registers. Spec. i-f 1.
An understanding of the invention can be derived from a reading of
exemplary claim 1, which is reproduced below:
1. A method comprising:
mapping to system memory control and status registers
of a coherent Input/Output device coupled to a host system bus;
and
providing direct memory access to the memory mapped
control and status registers in the system memory by a CPU that
is coupled to the host system bus.
REFERENCE
The Examiner relies on the following prior art:
Nishimukai us 5,509, 133 Apr. 16, 1996
REJECTION
Claims 1-27 stand rejected under 35 U.S.C. § 102(b) as anticipated by
Nishimukai. Final Act. 2-6.
1 Our decision makes reference to Appellant's Reply Brief ("Reply Br.,"
Nov. 27, 2013), and Appellant's Appeal Brief ("App. Br.," filed July 22,
2013), the Examiner's Answer ("Ans.," mailed Sept. 27, 2013), and Final
Office Action ("Final Act.," mailed Feb. 20, 2013).
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Appeal2014-002197
Application 12/217,089
ISSUE
The issue of whether the Examiner erred in rejecting claims 1-27
under 35 U.S.C. § 102(b) as anticipated byNishimukai turns on whether
Nishimukai discloses (a) a "coherent Input/Output device coupled to a host
system bus," as recited in independent claims 1 and 14; and (b) a "host
system bus," as recited in independent claims 1 and 14.
ANALYSIS
The Examiner finds Nishimukai's Input/Output (I/O) device, which is
coupled to a host system bus via I/O control circuits, discloses a "coherent
Input/Output device coupled to a host system bus," as recited in claims 1 and
14. Final Act. 2; Ans. 2, 6-7. Appellant argues that Nishimukai's I/O
device is not a coherent I!O device because Nishimukai' s I/O device is not
directly coupled to a host system. App. Br. 6-7; Reply Br. 3--4. According
to Appellant, a coherent I/O device must be in direct physical or electrical
contact with the host system. App. Br. 6-7; Reply Br. 2--4. Appellant
argues that "a coherent I/O device is explicitly defined in the Specification
as a device that is 'directly coupled' to the host system bus." App. Br. 7.
Appellant bases this argument on paragraph 2 of Appellant's Specification,
which recites that an "I/O device that is directly coupled to the host system
bus is referred to as a coherent I/O (CIO) device."
We disagree with Appellant. Although paragraph 2 indicates that an
I/O device that is directly coupled to a host system bus is referred to as a
CIO device, we are not persuaded that the Specification discloses that every
CIO must be directly coupled to a host system bus because the Specification
also discloses that the term "coupled" does not require that elements are in
direct contact with each other. See Spec. i-fi-12, 28. Specifically, Appellant's
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Appeal2014-002197
Application 12/217,089
argument is inconsistent with the Specification's definition of the term
"coupled." The disputed limitation in claims 1 and 14 recites a "coherent
Input/Output device coupled to a host system bus." The Specification
discloses two alternative definitions for the term "coupled." Spec. i-f 28. The
term "coupled" includes both "two or more elements [that] are in direct
physical or electrical contact" and "two or more elements [that] are not in
direct contact with each other, but yet still co-operate or interact with each
other." Id. (emphasis added). Thus, we agree with the Examiner that the
claim term "coupled" should not be interpreted as directly coupled, as
Appellant contends. Ans. 6-7. Accordingly, we do not find error on the
part of the Examiner in finding that Nishimukai discloses a "coherent
Input/Output device coupled to a host system." See id. (citing Nishimukai
3:57--4:14, 5:10-7:65).
Appellant also argues Nishimukai fails to disclose a "host system
bus," as recited in independent claims 1 and 14. App. Br. 6-7; Reply Br. 3.
Specifically, Appellant argues that the system bus ofNishimukai is not a
host system bus because it is not designed to couple to CPU-type devices.
Id.
We do not find Appellant's argument persuasive. The Examiner finds
Nishimukai discloses a CPU that is coupled to a host system bus in that the
data in the control register or the status register is sent by way of the bus to
the CPU. Ans. 7-8. We agree with the Examiner that Nishimukai discloses
data sent to the CPU via the bus. Id.; see Nishimukai 7:35-8:30. The data
transmission between the CPU and the bus requires an electrical connection.
See Nishimukai 4:56-5: 10, Fig. 5. Therefore, the CPU and bus of
Nishimukai are "coupled" because they "co-operate or interact with each
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Appeal2014-002197
Application 12/217,089
other" to transmit data. Thus, we are not persuaded that the N ishimukai bus
is not a host system bus because we find that the bus is coupled to a CPU.
Accordingly, we sustain the Examiner's rejection of independent
claims 1 and 14, and dependent claims 2-13 and 15-27, which are not
argued separately by Appellant.
CONCLUSION
The Examiner did not err in rejecting claims 1-27 under 35 U.S.C.
§ 102(b) as anticipated by Nishimukai.
DECISION
To summarize, our decision is as follows: the rejection of claims 1-27
under 35 U.S.C. § 102(b) as anticipated by Nishimukai is affirmed.
AFFIRMED
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