Ex Parte Chidambarrao et al

Board of Patent Appeals and Interferences

Sep 21, 2009

11065061 (B.P.A.I. Sep. 21, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
_____________

Ex parte DURESETI CHIDAMBARRAO and
OMER H. DOKUMACI
_____________

Appeal 2009-0044501
Application 11/065,061
Technology Center 2800
______________

Decided: September 23, 2009
_______________

Before JOHN C. MARTIN, KARL D. EASTHOM, and
CARL W. WHITEHEAD, JR., Administrative Patent Judges.

MARTIN, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE

1 The real party in interest is International Business Machines Corporation.
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This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-6 and 21-33, which are all of the pending claims. Oral
argument was heard on September 10, 2009.
We have jurisdiction under 35 U.S.C. § 6(b). We affirm.

A. Appellants’ invention2
Appellants’ invention relates to methods for manufacturing
semiconductor devices by imposing tensile and compressive stresses in the
substrate. Specification ¶ 0002. More particularly, the invention employs
an SOI (silicon-on-insulator) type substrate structure. Id. at ¶ 0017.
Appellants’ Figure 2 is reproduced below.

Br. 2.
2 Because the Specification as filed does not include line numbers or
paragraph numbers, we refer instead to the Specification of corresponding
Patent Application Publication 2005/0142788.
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Figure 2 is the first of six figures (i.e., Figs. 2-7) depicting sequential
phases of the method according to an embodiment of Appellants’ invention.
Figure 2 shows an SOI substrate structure having a semiconductor
substrate 10,3 which is typically a silicon substrate, a buried oxide layer 12
formed on the substrate 10, and a semiconductor layer 14, which is typically
a silicon layer, formed on the buried oxide layer 12. Id. at ¶ 0017.
Figure 3 is reproduced below.

Figure 3 shows the structure after shallow trench isolation (STI)
regions 16 have been formed in portions of the semiconductor layer 14 to
isolate individual device regions from each other. Id.
Figure 6 is reproduced below.

3 Numerals 10 and 12 do not appear in any of the figures.
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Figure 6 shows the structure following ion implantation in a first
region 20 of an expansion element (e.g., O2) and ion implantation in a
second region 24 of a compression element (e.g., He, Ar, or other noble gas).
Id. at ¶ 0019-20. As shown in this figure, when annealing is performed, the
first region 20 is activated and the expansion element expands the area that
was previously occupied by the first region. Id. at ¶ 0021. This expansion
pushes up the portions of the oxide layer 12 and the semiconductor layer 14
that overly the expanded substrate region, thereby increasing tensile stress in
the surface portion of the semiconductor layer 14 overlying the expended
area. Id. Also, upon annealing, the second region 24 is activated and the
compression element shrinks the area which was previously occupied by the
second region. Id. This compression pulls down the portions of the oxide
layer 12 and the semiconductor layer 14 that overly the compressed substrate
region, thereby increasing compressive stress in the surface portion of the
semiconductor layer 14 overlying the compressed area. Id.
We understand the foregoing discussion to mean that the compressive
and tensile stresses in the semiconductor layer are measured in the direction
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of current flow in the channel region, i.e., in the horizontal direction in
Figure 6.
Figure 7 is reproduced below.

Figure 7 shows the structure after formation of gate oxide layers 28
and gates 30 on semiconductor layer regions 14. Id. at ¶ 0023. The
Specification further explains:
Although it is not shown here, further processing steps would
include forming N type source and drain regions in the NMOS
area to constitute an N type device and P type source and drain
regions in the PMOS area to constitute a P type device. Since the
N type device is formed on the portion of the semiconductor layer
14 that has tensile strain, the performance of the N type device is
significantly improved. Also, due to the compressive strain the
performance of the P type device is significantly improved.
Id. The Specification does not indicate that the gate electrodes of the NMOS
and PMOS devices are formed of different materials (e.g., n-doped or p-
doped materials) or that their gate oxide layers are formed of different
materials.

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B. The claims
The independent claims before us are claims 1 and 25. Claim 1,
which we will address first, reads as follows:
1. A method for manufacturing a semiconductor device,
comprising steps of:
forming a semiconductor layer on a substrate;
expanding a first region of the substrate to push up a first
portion of the semiconductor layer;
compressing a second region of the substrate to pull
down a second portion of the semiconductor layer;
forming an N type device over the first portion of the
semiconductor layer; and
forming a P type device over the second portion of the
semiconductor layer.
Claims App., Br. 30.

C. The references and rejections
The Examiner relies on the following references:
Doyle et al. (Doyle) US 6,228,694 B1 May 8, 2001
Wasshuber et al. (Wasshuber) US 2003/0111699 A1 June 19, 2003
Takemura et al. (Takemura) US 6,790,749 B2 Sep. 14, 2004
Claims 1-6 and 21-33 stand rejected under 35 U.S.C. § 103(a) for
obviousness over Doyle in view of Wasshuber.
Claims 1-6 and 21-33 also stand rejected under § 103(a) for
obviousness over Doyle in view of Takemura and Wasshuber.

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THE ISSUES
Appellants have the burden on appeal to show reversible error by the
Examiner in maintaining the rejection. See In re Kahn, 441 F.3d 977, 985-
86 (Fed. Cir. 2006) (“On appeal to the Board, an applicant can overcome a
rejection by showing insufficient evidence of prima facie obviousness or by
rebutting the prima facie case with evidence of secondary indicia of
nonobviousness.” (citation omitted)).
The principal issue before us is the breadth of the claim terms “N type
device” and “P type device.”

PRINCIPLES OF LAW
Application claims are interpreted as broadly as is reasonable and
consistent with the specification, In re Thrift, 298 F.3d 1357, 1364 (Fed. Cir.
2002), while “taking into account whatever enlightenment by way of
definitions or otherwise that may be afforded by the written description
contained in the applicant’s specification,” In re Morris, 127 F.3d 1048,
1054 (Fed. Cir. 1997).
Regarding obviousness rejections, an Examiner is required to provide
“articulated reasoning with some rational underpinning to support the legal
conclusion of obviousness” of the claimed subject matter. KSR Int’l Co. v.
Teleflex Inc., 550 U.S. 398, 418 (2007) (citation omitted). Although a
rejection may be based on
interrelated teachings of multiple patents; the effects of demands
known to the design community or present in the marketplace; and
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the background knowledge possessed by a person having ordinary
skill in the art, all in order to determine whether there was an
apparent reason to combine the known elements in the fashion
claimed,
id., in order “[t]o facilitate review, this analysis should be made explicit.”
Id. “[H]owever, the analysis need not seek out precise teachings directed to
the specific subject matter of the challenged claim, for a court can take
account of the inferences and creative steps that a person of ordinary skill in
the art would employ.” Id.

THE SCOPE AND MEANING OF
“N TYPE DEVICE” AND “P TYPE DEVICE”
The term “device” is used in two different ways in independent
claims 1 and 25. Comparing claim 1 to Appellants’ Figure 7, the
“semiconductor device” recited in the preamble clearly includes the recited
“substrate” (unnumbered), the oxide layer (unnumbered), “semiconductor
layer” 14 (having unshown source, drain, and channel regions), and the “N
type device” and “P type device” (gates 30 with or without gate oxide layer
regions 28). Although the recited “N type device” and “P type device”
correspond to gates 30 (with or without gate oxides 28), the materials used
form the gates and the gate oxides are not disclosed as being different (e.g.,
“N type” or “P type”) materials. As a result, the words “N type” and “P
type” in the claim terms “N type device” and “P type device” can reasonably
be construed to be simply referring to the fact that the gate electrodes (and
their oxide layers) are parts of an N type or P type device, namely, the
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NMOS and PMOS devices, each of which also includes semiconductor
region 14 containing source, drain, and channel regions. Thus, the claim
terms “N type device” and “P type device” do not imply that device material
that is formed over the semiconductor region is an N type or P type material.
As a result, claim 1 does not require the presence of an SOI (silicon-on-
insulation) substrate.

ANALYSIS OF THE REJECTIONS
A. Claims 1-6
Doyle discloses a method of utilizing implants in a substrate to induce
a mechanical stress in the substrate to modify the carrier mobility of a
transistor. Doyle, col. 1, ll. 9-13.
Figure 1 is reproduced below.

Figure 1 is a side cross-sectional view of an NMOS transistor known
in the art. Id. at col. 2, ll. 11-12. The conventional transistor 10 generally
includes a semiconductor generally comprising a silicon layer 16 having a
source 20 and a drain 18 separated by a channel region 22, with a thin oxide
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layer 14 separating a gate 12, generally comprising polysilicon, from the
channel region 22. Id. at col. 1, ll. 29-35.
Figures 2A and 2 B are reproduced below.

Figures 2A and 2B are side cross-sectional views of an NMOS
transistor under tensile stress and compressive stress, respectively. Id. at col.
2, ll. 12-15. Applying a tensile stress, as shown in Figure 2A, results in a
narrower channel region 24 and thus a smaller bandgap and increased
mobility. Id. at col. 3, ll. 27-30. Applying a compressive stress, as shown in
Figure 2B, results in a larger channel region 26 and thus a larger bandgap
and a decreased mobility. Id. at col. 3, ll. 30-33. Thus, the stress and
dimensional changes appear to be measured in the same direction that
Appellants measure those characteristics, i.e., in the current flow direction in
the channel region (horizontally in Figures 2A and 2B).
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One method of creating localized stresses in a semiconductor is
through the implantation of a substance (e.g., a gas) into the silicon
substrate, resulting in the formation of voids (also referred to as cavities,
openings, or bubbles) within the substrate. Id. at col. 3, ll. 44-49.
As explained below, depending on where the voids are formed, the
same type of implanted substance can impart either compressive or tensile
stress to a channel region.
Figures 7 and 10 are reproduced below.

Figure 7 is a side cross-sectional view of an NMOS device with voids
in the channel region creating a tensile stress therein. Id. at col. 2, ll. 29-31.
Figure 10 is a side cross-sectional view of a PMOS device with voids in the
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source and drain regions creating a compressive stress therein. Id. at col. 2,
ll. 37-39.
Figure 11 is reproduced below.

Figure 11 is a side cross-sectional view of an MOS device having
NMOS devices under tensile stress and PMOS devices under compressive
stress. Id. at col. 2, ll. 40-42. In this embodiment, the voids formed in the
channel region of the NMOS devices 102 cause NMOS devices 102 to be
under a tensile stress and also cause PMOS devices 104 to be under a
compressive stress. Id. at col. 5, ll. 20-25. Doyle does not disclose
implanting both tensile and compressive elements in respective regions of
the Figure 11 embodiment.
Doyle’s Figure 16 is reproduced below.

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Figure 16 is a side cross-sectional view of an NMOS device with
gaseous implants in the gate creating a tensile stress in the device. Id. at
col. 2, ll. 54-56. This figure shows voids 132 in gate 124. Id. at col. 5, ll.
47-48.
Although the silicon substrate in Doyle’s Figure 11 embodiment can
accurately be characterized as a substrate and also as a semiconductor layer,
it cannot be accurately characterized as a semiconductor layer that is formed
on a substrate, as required by claims 1 and 25. It is apparently for that
reason that the Examiner reads the recited “semiconductor layer” on Doyle’s
polysilicon gates (e.g., 62 in Fig. 7; unnumbered gates of devices 102 and
104 in Fig. 11) and reads the recited “substrate” on Doyle’s substrate (e.g.,
50 in Fig. 7; unnumbered substrate in Fig. 11). Answer 16.
The Examiner has taken two different positions regarding the recited
steps of forming an “N type device” and a “P type device” “over” the
semiconductor layer, i.e., Doyle’s gate electrodes. In the first ground of
rejection, the Examiner reads the recited “N type device,” “P type device,”
and “semiconductor layer” on the gate electrodes. See, e.g., Final Action 3
(“forming an N type device (NMOS gate electrode, 64,[4] 102, a part of
NMOS) over the first portion of the semiconductor layer 64, 102 . . .”). We
agree with Appellants that the language of claims 1 and 25 does not permit
the recited “N type device” and the “P type device” to be read on the same
component as the recited “semiconductor layer.” See Br. 10 (As correctly

4 As noted above, Doyle’s NMOS device 64 includes a gate 62.
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pointed out by Appellants, “element 64 of Doyle is not formed over itself,
and, therefore, cannot arguably read on both the recited N type device and
semiconductor layer, as seemingly alleged by the Examiner.”).
Regarding the first ground of rejection, Appellants additionally argue
that Doyle also fails to disclose forming anything over the gate, as is
necessary if the recited “semiconductor layer” is being read on the gate. See
id. at 8 (“As seen in FIG. 1 of Doyle, there is nothing formed over gate 12
(i.e., there is nothing formed over what the Examiner identifies as the
semiconductor laver.)”). This argument is unconvincing because it fails to
address the obviousness of modifying Doyle by forming gate contacts over
the gate electrodes, as shown by Wasshuber, which like Doyle discloses
using ion implantation to induce stress in selected regions of NMOS and
PMOS transistors. Wasshuber ¶ 0006.
Figure 1 of Wasshuber is reproduced below.

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Figure 1 is a side elevation view in section illustrating a portion of an
exemplary semiconductor device in accordance with Wasshuber’s invention.
Id. at ¶ 0011. Transistor 20 includes a gate oxide structure 30 formed over
the channel region 24, as well as a poly gate structure 31 and a conductive
gate contact structure 32 overlying the poly gate 31. Id. at ¶ 0019.
We conclude that it would have been obvious to modify Doyle by
forming gate contacts over the gate electrodes of MOS devices 102 and
PMOS devices 104 in Doyle’s Figure 11 embodiment. The gate contact of
an NMOS device 102 can be characterized as an “N type device” because it
is part of the NMOS transistor. As explained above, the claim term “N type
device” does not imply any particular type of material. The gate contact of a
PMOS device 104 similarly can be considered to be a “P type device.”
Because Wasshuber therefore suggests forming N type and P type devices
over Doyle’s gates (i.e., the recited “semiconductor layer”), it is not
necessary to address the Examiner’s alternative reliance, in the second
ground of rejection, on Takemura for a teaching of forming source and drain
regions over Doyle’s gate electrodes.5

5 Specifically, the Examiner found that “Takemura et al. teaches at fig. 8A-
8D, and col. 19, line 48 to col. 20, line 47, forming source/drain regions over
the semiconductor layer 702, [7]03” (Final Action 7-8) and concluded that
“[i]t would have been obvious to one having ordinary skill in the art at the
time the invention was made to have modified Doyle ‘694 process by
forming the source/drain regions of NMOS and PMOS devices over the
semiconductor layer as suggested by Takemura et al.” Id. at 8. Appellants
argue that the Examiner has not established “motivation for modifying
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Appellants further argue that the subject matter of claims 1 and 25 is
unobvious over Doyle in view of Wasshuber and Takemura because those
references do not suggest forming an N type device and a P type device over
different portions of the same gates. See Br. 8 (“There certainly is not an N
type device formed over a first portion of gate 12 and a P type device formed
over a second portion of gate 12. The same can be said for gates 62 and 124
(i.e., the other elements the Examiner identifies as the semiconductor
layer).”). For the following reasons, we find that the claim language “first
portion of the semiconductor layer” and “second portion of the
semiconductor layer” reads on the gates of Doyle’s NMOS devices 102 and
PMOS devices 104 as well as it reads on the semiconductor layer regions 14
of Appellants’ NMOS and PMOS transistors. All of the gates in Doyle’s
Figure 11 embodiment presumably were initially deposited as portions of a
single layer, of which portions were subsequently removed, thereby leaving
the individual gates shown in that figure. That process is similar to the
process steps used to form Appellants’ semiconductor regions 14. That is,
Appellants’ Figures 2-7 show that semiconductor layer regions 14 were
initially formed as part of a single layer (Fig. 2), of which portions were
subsequently removed and replaced by isolation trench material 16, leaving
individual semiconductor regions 14. Specification ¶ 0017.

Doyle to relocate the source and drain from under the gate to over the gate.”
Br. 25.

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Appellants additionally argue that Doyle fails to disclose “expanding
a first region of the substrate to push up a first portion of the semiconductor
layer” and “compressing a second region of the substrate to pull down a
second portion of the semiconductor layer” (emphasis added), as required by
claim 1. Appellants correctly point out that “[t]here is absolutely no mention
that the embodiments shown in FIGS. 5-18 result in a bending of the
substrate as shown in FIGS. 2A and 2B.” Br. 13. However, we are not
persuaded that the Examiner erred in finding that the bending (i.e.,
deformation) depicted in Figures 2A and 2B is necessarily present to some
extent in the embodiments depicted in the other figures. To the contrary,
Doyle equates the existence of stress with deformation. As noted by the
Examiner (Answer 34), Doyle explains that “[l]ocalized stresses in a
substrate cause deformation of the substrate.” Doyle, col. 3, ll. 18-19
(emphasis added). Also, in discussing Figures 2A and 2B, Doyle explains
that carrier mobility is a function of the length of the channel region, which
is a function of the stress on the channel region. Doyle, col. 3, ll. 27-33.
Doyle then equates the bending (i.e., deformation) depicted in those figures
with stress when explaining that “in both FIGS. 2A and 2B the amount of
localized stress has been greatly exaggerated for illustrative purposes only.”
Id. at col. 3, ll. 33-35 (emphasis added). Wasshuber similarly explains that
ion implantation causes either volumetric expansion or volumetric
contraction of the substrate, depending on the type of implanted species.
Wasshuber ¶ 0021. Consequently, it is our understanding that the
compressive and tensile stresses that are created in the channel regions by
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the voids in the embodiments depicted in Doyle’s Figures 5-18 are due to
changes in the lengths of the channel regions and that those length changes
are achieved by bending (i.e., pushing up or down) (1) the upper portions of
the substrate that contain the channel regions and (2) the gate electrodes (and
gate oxide layers) formed thereon.
For the foregoing reasons, and because the channel regions of NMOS
devices 102 and PMOS devices 104 in Doyle’s Figure 11 embodiment are
respectively under tensile and compressive stress, we find that the Examiner
was justified in finding that substrate surface regions and gates of NMOS
devices 102 will be pushed up, while the substrate surface regions and gates
of PMOS devices 104 will be pulled down. As result, the burden was
shifted to Appellants to demonstrate otherwise. See In re Schreiber,
128 F.3d 1473, 1478 (Fed. Cir. 1997) (“where the Patent Office has reason
to believe that a functional limitation asserted to be critical for establishing
novelty in the claimed subject matter may, in fact, be an inherent
characteristic of the prior art, it possesses the authority to require the
applicant to prove that the subject matter shown to be in the prior art does
not possess the characteristic relied on.” (citation omitted)). Appellants have
not provided any evidence in support of their argument that “[t]he
production of tensile and compressive stresses in the substrate does not
necessarily result in portions of the device being pushed up and pulled
down.” Br. 13.
Appellants’ argument that “Doyle never discloses, implies or suggests
using both an expansion element in a one region and a compression element
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in a different region of the substrate” (Br. 12) is unconvincing, at least with
respect to claim 1, because that claim does not require implantation of
compressive and expansion elements. As noted above, Doyle’s Figure 11
embodiment has tensile and compressive stresses in different regions of the
substrate even though only expansion elements are implanted.
Inasmuch as Appellants have failed to persuade us that the Examiner
erred in rejecting claim 1 for obviousness over Doyle in view of Wasshuber,
we are affirming the rejection of claim 1 and its dependent claims 2-6, which
are not separately argued.
Because the Examiner’s reliance on Takemura for a teaching of
forming an “N type device” and a “P type device” over Doyle’s gate
electrodes is unnecessary in view of Wasshuber’s disclosure of the forming
gate contacts on the gate electrodes, we are affirming the rejection of claims
1-6 for obviousness over Doyle in view of Wasshuber and Takemura
without further analysis of Takemura, which is essentially cumulative to
Wasshuber.
In the following discussion of the remaining rejected claims, the
phrase “the rejection” refers to both grounds of rejection.

B. Claims 21-24
Claim 21 reads:
21. The method of claim 1, wherein the step of
compressing the second region comprises a step of ion-
implanting a compression element in the second region of the
substrate.
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This claim limitation can be satisfied by modifying Doyle’s Figure 11
embodiment (as already modified to include gate contacts) as to employ
compressive elements in the compressive (i.e., PMOS) regions instead of or
in addition to providing expansion elements in the expansion (NMOS)
regions, as disclosed by Doyle.
The Examiner initially read this limitation on Doyle without relying
on Wasshuber. Final Action 3, 7. Appellants responded by arguing that
Doyle instead “teaches that compression is accomplished by implanting an
expansion element around a region to be compressed, such that the
expansion element pushes inward on the region to be compressed.” Br. 16.
The Examiner responded by relying on Wasshuber for a teaching of
implanting compression or expansion elements:
Wasshuber clearly teaches at para. 29, the implantation of the
regions 112a and 112b impacts the lattice structure of the silicon
in the first regions 112 of the substrate 114, resulting in
volumetric expansion or contraction thereof according to the
dosage, energy, and species type of the implantation process 117
to achieve any desired concentration of implanted species within
the silicon in the regions 112.
Answer 41. Appellants’ discussion of the rejection of claim 21 in the Reply
Brief does not address this position of the Examiner and thus fails to
demonstrate error.
We are therefore affirming the rejection of claim 21 and the rejection
of dependent claims 22-24, which are not separately argued.

C. Claim 30
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30. The method of claim 1, wherein:
the step of expanding the first region comprises ion-
implanting an expansion element in the first region of the
substrate and annealing to activate the expansion element; and
the step of compressing the second region comprises ion-
implanting a compression element in the second region of the
substrate and annealing to activate the compression element.
These claim limitations can be satisfied by modifying Doyle’s Figure
11 embodiment (as already modified to include gate contacts) by implanting
compression elements in the compression (PMOS) regions while retaining
the expansion elements in the expansion (NMOS) regions.
The Examiner initially relied on Doyle’s Figures 2B and 9-11 and
some related passages for these claim limitations (Final Action 3).
However, at pages 42-44 of the Answer, the Examiner additionally relies on
Wasshuber’s above-quoted disclosure (Wasshuber ¶ 0029) of implanting
compressive or expansion elements and also on Doyle’s disclosure that
[t]he substance to be implanted into the substrate may be any one
of or a combination of several different gases, including but not
limited to the noble gases. Oxygen or other implanted ions may
also be used in reactions to alter the internal region of the
substrate by way of specific volume or thermal expansion
differences (e.g., oxidized voids).
Doyle, col. 4, ll. 1-7. Appellants responded by arguing that
[t]he Examiner has provided no reasonable explanation as to why
a skilled artisan would have been prompted to modify Doyle to
replace the expansion element around the compressive region with
a compression element implanted in the compressive region,
which would achieve nothing more than what Doyle already
provides.
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Reply Br. 5. This argument is unconvincing because it misconstrues the
rationale of the rejection, which calls for implanting compressive elements
in the compressive (PMOS) regions while retaining the expansion elements
in the expansion (NMOS) regions. Furthermore, such a modification would
have been obvious because a person skilled in the art would have recognized
that such a modification will permit the amount of the compressive stress in
the compression (PMOS) regions to be increased over the amount of
compressive stress that is due to the expansion elements in the expansion
(NMOS) regions and thus will provide a greater degree of control over the
amount of compressive stress in the compression (PMOS) regions.
Regarding the requirement of claim 30 for annealing the expansion
and compressions elements, Appellants argue that
Doyle teaches annealing an expansion element in a first
region to create tensile stress in the first region. Doyle also
teaches annealing an expansion element around a second region to
produce compressive stress in the second region. However, Doyle
does not disclose annealing a compression element that is
implanted in the second region. Wasshuber does not disclose
annealing at all.
Reply Br. 6. Although neither Doyle nor Wasshuber discloses annealing of
a compression element, this argument is unpersuasive because Appellants do
not argue in their briefs or assert in their Specification that it was unknown
in the art to anneal MOS devices that have been implanted with compression
elements. A rejection for obviousness can properly be based on “the
background knowledge possessed by a person having ordinary skill in the
art.” KSR, 550 U.S. at 418.
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The rejection of claim 30 is therefore affirmed.

D. Claim 31
Claim 31, which adds an oxide layer, reads as follows:
31. The method of claim 30, wherein
the expanding the first region pushes up a first portion of
an oxide layer and the first portion of the semiconductor layer
thereby increasing tensile stress in the first portion if [sic] the
semiconductor layer, and
the compressing the second region pulls down a second
portion of the oxide layer and the second portion of the
semiconductor layer thereby increasing the compressive stress
in the second portion of the semiconductor layer.
Regarding the rejection of this claim, Appellants repeat some of their
claim 1 arguments, which are unconvincing for the reasons given above.
Appellants also argue that although the prior art device depicted in
Doyle’s Figure 1 includes a gate oxide layer 14, “it does not necessarily flow
from the teachings of Doyle that the NMOS and PMOS devices depicted in
FIGS. 4-18 include an oxide layer.” Reply Br. 7. Even though Doyle does
not describe the gates of Figure 7, 10, or 11 as being separated from the
substrate by an oxide layer, the Examiner correctly found that Doyle’s
NMOS and PMOS transistors by definition include an oxide layer.
Answer 45. See Wasshuber ¶ 0002 (explaining that “MOS-FET” stands for
“metal-oxide-semiconductor field-effect transistor”).
Also, for the same reasons that the Examiner was justified in finding
that the substrate surface regions and gates of NMOS devices 102 inherently
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will be pushed up, while the substrate surface regions and gates of PMOS
devices 104 will be pulled down, the same is true of the associated oxide
layer regions. We are therefore not persuaded by Appellants’ argument that
“there is no teaching that the expanding the first region pushes up a first
portion of an oxide layer . . . and the compressing the second region pulls
down a second portion of the oxide layer.” Reply Br. 8 (emphasis omitted).
The rejection of claim 31 is therefore affirmed.

E. Claims 25-28 and 32
Independent claim 25 reads as follows:
25. A method for manufacturing a semiconductor device,
comprising steps of:
forming a semiconductor layer on a substrate;
expanding a first region of the substrate to provide a
tensile stress in the semiconductor layer;
compressing a second region of the substrate to provide a
compressive stress in the semiconductor layer by ion-
implanting a compression element in the second region and
annealing to activate the compression element;
forming an N type device over the semiconductor layer
over the first region of the substrate; and
forming a P type device over the semiconductor layer
over the second region of the substrate.
Claim 25 does not recite any expansion elements and thus can be
satisfied by modifying Doyle’s Figure 11 embodiment (as already modified
to include gate contacts) as to employ compressive elements in the
compressive (i.e., PMOS) regions instead of or in addition to providing
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expansion elements in the expansion (NMOS) regions, as disclosed by
Doyle.
Regarding the implantation of compression elements, the Examiner
relies on the same parts of Doyle that are relied on in the rejection of claim
30 and on Wasshuber’s disclosure of implanting expansion or compression
elements. Answer 47, 50. Appellants argue that
Doyle does not disclose compressing a second region of the
substrate to provide a compressive stress in the semiconductor
layer by ion-implanting a compression element in the second
region. Instead, Doyle discloses compressing a second region by
implanting an expansion element around the second region.
Reply Br. 9. This argument is unconvincing because it fails to address the
fact that the claim can be satisfied by omitting the expansion elements in the
expansion (NMOS) regions and instead implanting compression elements in
the compression (PMOS) regions, which modification predictably will
preserve the compressive stress in NMOS devices and the compressive stress
in the PMOS devices. “[W]hen a patent claims a structure already known in
the prior art that is altered by the mere substitution of one element for
another known in the field, the combination must do more than yield a
predictable result.” KSR, 550 U.S. at 416.
Appellants also argue that the references fail to disclose annealing of
compression elements. Reply Br. 10. However, Appellants do not deny that
it was known to anneal a device after implantation of compression elements,
Appeal 2009-004450
Application 11/065,061

26
such as those disclosed by Wasshuber.6 A rejection for obviousness can
properly be based on the “the background knowledge possessed by a person
having ordinary skill in the art.” Id. at 418.
The rejection of claim 25 is therefore affirmed, as is the rejection of
dependent claims 26-28 and 32, which are not separately argued.

F. Claim 29
Claim 29 reads:
29. The method of claim 28, wherein the expansion
element is O2 and the compression element is He, Ar, or noble
gas.
Wasshuber characterizes oxygen as an expansion element in
paragraph 0021 (“where germanium or oxygen is implanted in the regions
12, . . . a volumetric expansion results in the regions 12”).
Regarding the claim requirement that the compression element be He,
Ar, or a noble gas,7 Appellants correctly point out that Wasshuber fails to
disclose that the compression elements discussed therein can take the form
of a noble gas. Reply Br. 10. Appellants also correctly note that Doyle’s
statement that “[t]he substance to be implanted into the substrate may be any
one of or a combination of several different gases, including but not limited

6 Doyle discloses annealing to alter the size of voids created by implanted
noble gas He and thereby alter the stress. Doyle, col. 4, ll. 23-64.
7 Inasmuch as helium and argon are noble gases, we understand the claim
language “He, Ar, or noble gas” to mean “He, Ar, or another noble gas.”

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27
to the noble gases” (Doyle, col. 4, ll. 1-3) does not indicate that the noble
gases can serve as compression elements. Id.
Nevertheless, we are affirming the rejection of claim 29 because
Appellants do not argue in their briefs or assert in their Specification that it
was unknown to employ a noble gas as a compression element. A rejection
for obviousness can properly be based on “the background knowledge
possessed by a person having ordinary skill in the art.” KSR, 550 U.S.
at 418.

G. Claim 33
Claim 33, which depends on claim 25 through claim 32, is similar to
claim 31 (addressed above) in that it recites an oxide layer:
33. The method of claim 32, wherein
the expanding the first region pushes up a first portion of
an oxide layer and a first portion of the semiconductor layer
thereby increasing tensile stress in the first portion of the
semiconductor layer, and
the compressing the second region pulls down a second
portion of the oxide layer and a second portion of the
semiconductor layer thereby increasing the compressive stress
in the second portion of the semiconductor layer.
The rejection of this claim is affirmed for the same reasons as the
rejection of claim 31.

Appeal 2009-004450
Application 11/065,061

28
SUMMARY
The rejection of claims 1-6 and 21-33 under 35 U.S.C. § 103(a) for
obviousness over Doyle in view of Wasshuber is affirmed.
The rejection of claims 1-6 and 21-33 under § 103(a) for obviousness
over Doyle in view of Takemura and Wasshuber is also affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136. See 37 C.F.R.
§ 1.136(a)(1)(iv).

AFFIRMED

babc

Andrew M. Calderon
Greenblum and Bernstein, P.L.C.
1950 Roland Clarke Place
Reston, VA 20191