Ex Parte Chiang et al

Patent Trial and Appeal Board

Dec 13, 2016

13887485 (P.T.A.B. Dec. 13, 2016)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/887,485 05/06/2013 Meei-Ling Chiang 1458-0522 1060
102347 7590 12/15/2016
Polansky & Associates, P.L.L.C.
12600 Hill Country Blvd
Suite R-275
Austin, TX 78738
EXAMINER
CHENG, DIANA
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
12/15/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ppolansky@patentwerks.net
admin @ patent werks. net
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MEEI-LING CHIANG, BOON-AIK ANG,
and DENNIS FISCHETT, JR.
Appeal 2015-007377
Application 13/887,485
Technology Center 2800
Before TERRY J. OWENS, LINDA M. GAUDETTE, and
DEBRA L. DENNETT, Administrative Patent Judges.
OWENS, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
The Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’
rejection of claims 1—8 and 14—20. We have jurisdiction under
35 U.S.C. § 6(b).
The Invention
The Appellants claim a phase locked loop system and a method for
measuring a bandwidth of a phase locked loop. Claim 1 is illustrative:
1. A phase locked loop system comprising:
a phase locked loop having a reference clock input, a
voltage controlled oscillator (VCO) clock output, and a
feedback clock output; and
Appeal 2015-007377
Application 13/887,485
a calibration circuit for providing a reference clock signal
to said reference clock input of said phase locked loop,
inducing first and second phase disturbances between said
reference clock signal and a feedback clock signal, measuring
respective first and second zero crossing times of a phase error
between said reference clock signal and said feedback clock
signal, and estimating a bandwidth of said phase locked loop in
response to said first and second zero crossing times.
The Reference
Galloway US 7,042,252 B2 May 9,2006
The Rejection
Claims 1—8 and 14—20 stand rejected under 35 U.S.C. § 102(a)(1)
over Galloway.
OPINION
We reverse the rejection. We need address only the independent
claims (1 and 14). Those claims require estimating a bandwidth of a phased
lock loop in response to first and second zero crossing times.
“Anticipation requires that every limitation of the claim in issue be
disclosed, either expressly or under principles of inherency, in a single prior
art reference.” Corning Glass Works v. Sumitomo Elec. U.S.A., Inc., 868
F.2d 1251, 1255—56 (Fed. Cir. 1989). ‘“[Djuring examination proceedings,
claims are given their broadest reasonable interpretation consistent with the
specification.’” In re Translogic Tech. Inc., 504 F.3d 1249, 1256 (Fed. Cir.
2007) (quoting In re Hyatt, 211 F.3d 1367, 1372 (Fed. Cir. 2000)).
Regarding the meaning of “bandwidth” the Appellants’ Specification
states (Spec. 124):
The bandwidth of PLL [phase locked loop] 100 is
generally defined as the frequency where PLL 100 begins to
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Appeal 2015-007377
Application 13/887,485
lose lock with the REFCLK [reference clock] signal, and is
indicated for each of waveforms 201, 220, and 230 [Fig. 2], by
the -3 dB point (P2) on the vertical axis of graph 200. A
particular bandwidth corresponds to the phase error, settling
time, and jitter tracking capability of PFF 100. Bandwidth is a
measure of the ability of PFF 100 to track the REFCFK signal
and the associated jitter of the REFCFK signal.
In response to the Appellants’ assertion that “there is no indication
that Galloway ever estimates the bandwidth of PFF 10, nor does the word
‘bandwidth’ ever appear in Galloway” (App. Br. 13), the Examiner finds
(Ans. 8):
Galloway discloses in Col. 5, lines 36—56 that “the DC offset
causes ... the medial transition point [to become] a median
transition region” (i.e. bandwidth). The median transition
region demonstrates the bandwidth of the phase locked loop
because the region shows the width of the band in which the
phase locked loop is stable. See Fig. 5B. That is, “the PFF is
stable if the transistor sample location (and therefore the phase
of the recovered clock) is anywhere within the median
transition region as indicated by FIGS. 5A, 5B, and 6.
The meaning the Examiner gives to the Appellants’ claim term
“bandwidth” does not appear to be within the broadest reasonable
interpretation of that term consistent with the Specification. The Examiner
does not address the Appellants’ Specification’s disclosure and establish that
the broadest reasonable interpretation of “bandwidth” consistent with that
disclosure encompasses the Examiner’s interpretation of that term. Nor does
the Examiner establish that Galloway discloses estimating a bandwidth, let
alone estimating it in response to first and second zero crossing times.
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Appeal 2015-007377
Application 13/887,485
Hence, the Examiner has not established that Galloway discloses,
either expressly or inherently, each limitation of the Appellants’ claims.
Accordingly, we reverse the rejection.
DECISION/ORDER
The rejection of claims 1—8 and 14—20 under 35 U.S.C. § 102(a)(1)
over Galloway is reversed.
It is ordered that the Examiner’s decision is reversed.
REVERSED
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