Ex Parte Chern et al

Patent Trial and Appeal Board

Jun 29, 2016

13859413 (P.T.A.B. Jun. 29, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/859,413 04/09/2013 Chan-Hong CHERN
95496 7590 07/01/2016
Hauptman Ham, LLP (TSMC)
2318 Mill Road
Suite 1400
Alexandria, VA 22314
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
T5057-Y282A 8532
EXAMINER
WELLS, KENNETH B
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
07/01/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
tsmc@ipfirm.com
sramunto@ipfirm.com
pair_lhhb@firsttofile.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CHAN-HONG CHERN, FU-LUNG HSUEH,
CHIH-CHANG LIN, YUWEN SWEI, and MING-CHIER HUANG
Appeal2014-007279
Application 13/859 ,413
Technology Center 2800
Before JASON V. MORGAN, JOSEPH P. LENTIVECH, and
SHARON PENICK, Administrative Patent Judges.
LENTIVECH, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 seek our review under 35 U.S.C. § 134(a) of the
Examiner's final rejection of claims 1--4, 8-11, and 15-19. The Examiner
objects to claims 5-7, 12-14, and 20 as being dependent upon a rejected
base claim, but has indicated these claims would be allowable if rewritten in
independent form including all the limitations of the base claim and any
intervening claims. See Ans. 8. We have jurisdiction over the pending
claims under 35 U.S.C. § 6(b ).
We AFFIRM.
1 According to Appellants, the real party in interest is Taiwan
Semiconductor Manufacturing Company LTD. App. Br. 2.
Appeal2014-007279
Application 13/859,413
STATEMENT OF THE CASE
Appellants 'Invention
Appellants' invention generally relates to a level shifter architecture
or system. Spec. i-f 2. To reduce power consumption and enhance the
performance per unit area, integrated circuits, e.g., central processing unit
(CPU), graphics processing unit (GPU), system on chip (SOC), may reduce
the core operating voltage. Spec. i-f 3. The surrounding chips or peripheral
circuits, e.g., input-output (I/O), may still operate at higher voltages. Id.
Level shifting is used to accommodate voltage differences from the core
logic to the I/O interfaces. Id. Claims 1 and 17, which are representative,
read as follows:
1. An integrated circuit, comprising:
a pre-driver configured to receive a first high supply
voltage and to generate an input signal; and
at least one post-driver configured to receive at least one
second high supply voltage and to receive the input signal,
wherein the at least one second high supply voltage is different
from the first high supply voltage, the at least one post-driver
compnsmg:
an input node configured to receive the input signal;
an output node configured to output an output signal;
a pull-up transistor, wherein the pull-up transistor is
configured to be in a conductive state during an entire period of
operation;
a pull-down transistor; and
at least one diode-connected device coupled between the
pull-down transistor and the output node,
wherein each post-driver of the at least one post-driver is
configured to receive the input signal having a first voltage level
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corresponding to a high logic level, and to supply the output
signal having a second voltage level corresponding to a high
logic level, the second voltage level being higher than the first
voltage level.
17. A level shifter, comprising:
an input node configured to receive an input signal;
an output node configured to output an output signal;
a pull-up transistor, wherein the pull-up transistor is
configured to be in a conductive state during an entire period of
operation;
a pull-down transistor;
at least one diode-connected device coupled between the
pull-down transistor and the output node; and
a dynamic biasing circuit configured to control the pull-up
transistor, wherein the dynamic biasing circuit comprises:
a first transistor of a first type;
a first transistor of a second type; and
at least one second diode-connected device connected
between the first transistor of the first type and the first transistor
of the second type,
wherein the level shifter is configured to receive the input
signal having a first voltage level corresponding to a high logic
level, and to supply the output signal having a second voltage
level corresponding to a high logic level, the second voltage level
being higher than the first voltage level.
References and Rejections
Claims 1and3 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Tran et al. (US 6,784,690 B2; Aug. 31, 2004) ("Tran"). Final
Act. 2-3.
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Application 13/859,413
Claims 1, 3, 4, 9, 17, and 19 stand rejected under 35 U.S.C. § 102(e)
as being anticipated by Pasqualini (US 7,863,962 B2; Jan. 4, 2011). Final
Act. 3-5.
Claims 1, 3, 4, 9, 17, and 19 stand rejected under 35 U.S.C. § 102(e)
as being anticipated by Thorp et al. (US 7,696,805 B2; Apr. 13, 2010)
("Thorp"). Final Act. 5---6.
Claims 2, 8, 10, 11, 15, 16, and 18 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Pasqualini. Final Act. 7-8.
Claims 2, 8, 10, 11, 15, 16, and 18 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Thorp. Final Act. 8.
ANALYSIS
§ 102 Rejection based on Tran
Issue: Did the Examiner err in finding that Tran discloses "at least
one post-driver configured to receive at least one second high supply voltage
and to receive the input signal, wherein the at least one second high supply
voltage is different from the first high supply voltage," as recited in claim 1?
Appellants further contend Tran fails to disclose the disputed
limitation because "Tran fails to explicitly or inherently disclose any
operating voltage other than operating voltage VDDI." App. Br. 10; see
also Reply Br. 4. Appellants further contend "[t]he Examiner failed to
provide any evidence or explanation to support an assertion that [] supply
voltage VDDl, supplied to the post-driver, is different from the supply
voltage provided to the unillustrated circuitry [of Figure 3A]." Id.
We do not find Appellants' contention persuasive. The Examiner
finds, and we agree, Tran discloses "a first lower operating voltage VDD2,
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which is the power supply of the core microprocessor circuitry which
outputs signal Din ... and a second higher operating voltage VDD 1, which
is the power supply of circuits 20 and 16." Ans. 4 (citing Tran 1 :49---67).
The Examiner finds, and we agree, Tran further discloses that VDDl is
greater than VDD2. Id. Tran, therefore, discloses the disputed limitation.
We do not consider Appellants' contention that the rejection should be
reversed because "[i]n the Answer, the Examiner changed the factual basis
for the rejection for the very first time in a new ground of rejection." Reply
Br. 4. Any request to seek review of the Examiner's failure to designate a
rejection as a new ground of rejection in an Examiner's answer must be by
way of a petition to the Director of the US PTO under 3 7 C.F .R. § 1.181
(2013). 37 C.F.R. § 41.40(a) (2013). Further, the petition must be filed
within two months from the entry of the Examiner's Answer and before the
filing of any Reply Brief. Id. Appellants' failure to timely file such a
petition within the prescribed period constitutes a waiver of any arguments
that the rejection must be designated as a new ground of rejection. Id.
We are also not persuaded by Appellants' contention that the rejection
is improper because "the Examiner is relying on two different embodiments
of the Tran reference in an anticipation rejection." Reply Br. 6. Particularly,
Appellants contend the Examiner relies on the embodiments shown in
Figures 2A and 3A of Tran and "Tran states, on the one hand, that Figure 2A
is a schematic diagram of a driver and, on the other hand, that Figure 3A is a
schematic diagram of another driver." Reply Br. 6 (citing Tran 4: 1-8).
Tran discloses "FIG. 2A is a schematic diagram of a driver 16 which may be
employed in one of the IO devices of microprocessor 10." Tran 1:32-34.
Tran further discloses "FIG. 3A is a schematic diagram of driver 16 with P
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channel FETs 34--36 and N channel FETs 44--48 added thereto." Tran 2:51-
53. Tran's description of the two supply voltages VDm and VDm relates to
the operation of the voltage level converter circuit 20, which is common to
both embodiments of the driver. See Tran, Figs. 2A, 3A. As such, we are
not persuaded the Examiner erred in finding Tran discloses the disputed
limitation.
For the foregoing reasons, we are not persuaded the Examiner erred in
rejecting claim 1, and claim 3 which depends from claim 1 and is not
separately argued, under 35 U.S.C. § 102(b) as being anticipated by Tran.
§ 102 Rejection based on Pasqualini
CLAIM 1
Issue: Did the Examiner err in finding that Pasqualini discloses "a
pull-up transistor, wherein the pull-up transistor is configured to be in a
conductive state during an entire period of operation," as recited in claim 1?
Appellants contend Pasqualini fails to disclose the disputed limitation.
App. Br. 14--15; Reply Br. 7-9. According to Appellants, Pasqualini
discloses that turning on PMOS transistor Pl I and turning off transistor NI
causes PMOS transistor P7 to tum off. App. Br. 14 (citing Pasqualini 7:23-
24). Appellants contend because Pasqualini discloses turning off PMOS
transistor P7, which is relied upon by the Examiner for disclosing the
claimed pull-up transistor, Pasqualini does not disclose that the pull-up
transistor is configured to be in a conductive state during an entire period of
operation, as required by claim 1. App. Br. 14--15.
The Examiner finds the broadest reasonable interpretation of "an
entire period of operation" is "the entire period of operation when ...
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Pasqualini's transistor P7 is conducting." Ans. 5. Based on this
interpretation, the Examiner finds Pasqualini's PMOS transistor P7 discloses
the claimed "pull-up resistor."
In response, Appellants contend the Examiner's findings in the
Answer constitute a new ground of rejection and that the Examiner's
interpretation is unreasonably broad because it "effectively removes the
phrase 'during an entire period of operation' from the claim language."
Reply Br. 7-10.
We do not consider Appellants' contentions regarding the Examiner's
findings constituting a new ground of rejection because, as discussed supra,
any request to seek review of the Examiner's failure to designate a rejection
as a new ground of rejection in an Examiner's answer must be by way of a
petition to the Director of the USPTO under 37 C.F.R. § 1.181. Id.
We do not find Appellants' contentions that the Examiner's
interpretation of "an entire period of operation" is unreasonably broad
because Appellants' Specification does not define the phrase, and
"[ c ]onstruing claims broadly during prosecution is not unfair to the applicant
... because the applicant has the opportunity to amend the claims to obtain
more precise claim coverage." In re Amer. Acad. of Sci. Tech Ctr., 367 F.3d
1359, 1364 (Fed. Cir. 2004). Appellants essentially contend that "an entire
period of operation" refers to a particular entire period of operation (e.g.,
when the input signal corresponds to a logical "1" and when the input signal
corresponds to a logical "O" (see Spec. i-fi-120-21 )). However, claim 1 does
not specify any particular reference for the operation referenced by the
"entire period of operation" during which the pull-up transistor is required to
be configured to be in a conductive state during. Instead, claim 1 merely
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recites that "the pull-up transistor is configured to be in a conductive state
during an entire period of operation." See Claim 1. As such, we are not
persuaded the Examiner's interpretation is unreasonable.
For the foregoing reasons, we are not persuaded the Examiner erred in
rejecting claim 1, and claims 3, 4, and 9 which depend from claim 1 and are
not separately argued (see App. Br. 15), under 35 U.S.C. § 102(e) based on
Pasqualini.
CLAIM 17
Issue 1: Did the Examiner err in finding that Pasqualini discloses "a
pull-up transistor, wherein the pull-up transistor is configured to be in a
conductive state during an entire period of operation," as recited in claim
17?
Appellants contend the Examiner erred in finding Pasqualini discloses
the disputed limitation "for reasons analogous to those set forth above with
respect to claim 1." App. Br. 15. Accordingly, we are not persuaded the
Examiner erred in finding Pasqualini discloses this limitations for the
reasons discussed supra with respect to the rejection of claim 1 under 35
U.S.C. § 102(e) based on Pasqualini.
Issue 2: Did the Examiner err in finding that Pasqualini discloses "a
dynamic biasing circuit configured to control the pull-up transistor," as
recited in claim 1 7?
Appellants contend:
In the rejection of claim 1, the Examiner stated that "the recited
'pull-up transistor' reads on either transistor P7 (or, alternatively,
anyone of transistor P5, P6, or PI2)." See FOA, at page 4.
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Application I3/859,4I3
Transistor P7 cannot reasonably be interpreted as corresponding
to the recited pull-up transistor for at least the reasons set forth
above with respect to claim I. Further, elements P5 and P6 are
diode-connected transistors which are not described as being
controlled by a biasing circuit. See, Pasqualini, at Figure 6. In
addition, element PI2 receives a reference voltage Vref at a gate
thereof. See Pasqualini, at Figure 6. Pasqualini fails to explicitly
or inherently describe how the reference voltage Vref is
generated. Still further, one of ordinary skill in the art would not
reasonably interpret a circuit which is used to generate a
reference voltage as a "dynamic biasing circuit" as recited in
claim I 7. Thus, none of the elements P5, P6 or PI 2 are explicitly
or inherently described as being capable of being controlled by
the recited dynamic biasing circuit.
App. Br. I5-I6.
The Examiner finds "the recited dynamic biasing circuit reads on the
combination of transistors PI I, P2I and NI." Final Act. 5. Pasqualini
discloses "because PMOS transistor PI I is turned on and NMOS transistor
NI is turned off, PMOS transistor PI I will charge up the gate of PMOS
transistor P7, turning transistor P7 off'' Pasqualini 7:21--'24 (emphasis
omitted). As such, Pasqualini discloses a dynamic biasing circuit that is
configured to control PMOS transistor P7. Because, as discussed supra, we
find the starting premise of Appellants' contention to be unpersuasive (that
Pasqualini's PMOS transistor P7 cannot disclose the claimed pull-up
transistor), we likewise find the conclusions drawn from that premise (that
the combination of transistors PI I, P2 I, and NI cannot disclose the claimed
dynamic biasing circuit) to be unpersuasive of Examiner error. Accordingly,
we are not persuaded the Examiner erred in finding Pasqualini discloses the
disputed limitation.
For the foregoing reasons, we are not persuaded the Examiner erred in
rejecting claim I 7, and claim I9, which depends from claim I 7 and is not
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separately argued (see App. Br. 16), under 35 U.S.C. § 102(e) based on
Pasqualini.
§ 102 Rejection based on Thorp
Appellants contend the Examiner erred in finding Thorp discloses the
disputed limitation because:
The Examiner asserted that Thorp' s element 121 corresponds to
the recited pull-up transistor. Thorp fails to disclose element 121
is configured to be in a conductive state during an entire period
of operation. Thorp states the following: "turning off PMOS
transistor 121 to thereby allow the discharge path to completely
discharge the Q output node 115." See Thorp, at column 3, lines
16-17. Thorp explicitly states that element 121 is not capable of
being in a conductive state during an entire period of operation.
App. Br. 19. Appellants contend the Examiner's construction of "entire
period of operation" as referring to is "the entire period of operation when
... Pasqualini's transistor P7 is conducting" (Ans. 5) as being a new ground
of rejection and unreasonably broad for the reasons discussed supra with
respect to claim 1. Reply Br. 10.
As Appellants' contentions are essentially the same as those discussed
supra with respect to the rejection of claim 1under35 U.S.C. § 102(e) based
on Pasqualini, we are not persuaded the Examiner erred in finding Thorp
discloses the disputed limitation for the same reasons.
Accordingly, we are not persuaded the Examiner erred in rejecting
claim 1under35 U.S.C. § 102(b) based on Thorp.
Regarding the rejection of claims 3, 4, 9, 17, and 19, because
Appellants have either not presented separate patentability arguments or
have reiterated substantially the same arguments as those previously
discussed for patentability of claim 1 above (see App. Br. 19--20), claims 3,
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4, 9, 17, and 19 fall therewith. See 37 C.F.R. § 41.37(c)(l)(iv) (2013).
§ 103 Rejections
Regarding the rejection of claims 2, 8, 10, 11, 15, 16, and 18 under 35
U.S.C. § 103(a) based on Pasqualini and the rejection of claims 2, 8, 10, 11,
15, 16, and 18 under 35 U.S.C. § 103(a) based on Thorp, Appellants rely on
the patentability arguments previously discussed regarding the rejection of
claim 1under35 U.S.C. § 102(e) based on Pasqualini and the rejection of
claim 1under35 U.S.C. § 102(b) based on Thorp, respectively. See App.
Br. 20-25. Accordingly, we are not persuaded the Examiner erred in
rejecting claims 2, 8, 10, 11, 15, 16, and 18 under 35 U.S.C. § 103(a) based
on Pasqualini and under 35 U.S.C. § 103(a) based on Thorp for the reasons
discussed supra with respect to the rejection of claim 1 under 35 U.S.C.
§ 102(e) based on Pasqualini and the rejection of claim 1under35 U.S.C.
§ 102(b) based on Thorp.
DECISION
We affirm the Examiner's rejections of claims 1--4, 8-11, and 15-19.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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