12984703 (P.T.A.B. Dec. 15, 2016)

Ex Parte Cheng et al

Patent Trial and Appeal BoardDec 15, 2016

12984703 (P.T.A.B. Dec. 15, 2016)

United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/984,703 01/05/2011 Chun-Fai CHENG T5057-B358U 2827 95496 7590 12/19/2016 Hauptman Ham, LLP (TSMC) 2318 Mill Road Suite 1400 Alexandria, VA 22314 EXAMINER VU, DAVID ART UNIT PAPER NUMBER 2818 NOTIFICATION DATE DELIVERY MODE 12/19/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): tsmc@ipfirm.com sramunto @ ipfirm.com pair_lhhb @ firsttofile. com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte CHUN-FAI CHENG, KA-HING FUNG, LI-PING HUANG, and WEI-YUAN LU Appeal 2015-007411 Application 12/984,703 Technology Center 2800 Before TERRY J. OWENS, GEORGE C. BEST, and LILAN REN, Administrative Patent Judges. OWENS, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE The Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’ rejection of claims 9—28. We have jurisdiction under 35 U.S.C. § 6(b). The Invention The Appellants claim a method for fabricating a p-type field effect transistor. Claim 9 is illustrative: 9. A method for fabricating a p-type field effect transistor, said method comprising: providing a dummy gate stack over a substrate; recessing the substrate to form source/drain (S/D) recess cavities in the substrate and adjacent to the dummy gate stack; Appeal 2015-007411 Application 12/984,703 selectively growing a strained material in the S/D recess cavities; performing a thermal process on the grown strained material to form source/drain (S/D) extensions conformably surrounding the S/D recess cavities; removing the dummy gate stack to form an opening exposing the substrate under the dummy gate stack; recessing the substrate exposed in the opening to form a channel recess cavity spaced apart from the S/D recess cavities; and forming a gate stack in the opening, said gate stack having a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. Mandelman Brask Cheng Wang Matsuo The References US 6,335,248 B1 Jan. 1,2002 US 7,858,481 B2 Dec. 28, 2010 US 8,022,488 B2 Sep. 20,2011 (filed Sep. 24, 2009) US 2011/0306170 A1 Dec. 15,2011 (filed Aug. 28, 2009) US 8,138,552 B2 Mar. 20, 2012 (filed Dec. 18, 2008) The Rejections The claims stand rejected under 35 U.S.C. § 103 as follows: claims 9, 3—17, and 19 over Brask in view of Wang, claims 21—28 over Brask in view of Wang and Matsuo, claims 10-12 over Brask in view of Wang and Cheng and claims 18 and 20 over Brask in view of Wang and Mandelman. OPINION We reverse the rejections. We need address only the independent claims (9, 21, and 27). Each of those claims requires performing a thermal process to form source/drain extensions conformally surrounding 2 Appeal 2015-007411 Application 12/984,703 source/drain recess cavities.1 To meet that claim requirement the Examiner relies upon the combination of Brask and Wang (Final Act. 2—3). Brask discloses a method for forming a PMOS transistor wherein source and drain regions (120) having tip extensions extending under a dummy gate (104) edge are formed by selectively depositing epitaxial boron doped Si or SiGe at 750-800 -C onto an undercut (114) extending under the dummy gate (104) (col. 5,11. 51—53, 59-62; col. 6,11. 1—10; Figs. 16, 17). “SiGe in the source/drain regions exerts compressive stress on the channel, which in turn results in enhanced mobility and improved transistor performance” (col. 6,11. 14—16). Wang discloses a method for forming a PMOS transistor comprising implanting source/drain areas with p-type dopant, etching the implanted regions (122) to remove Si and at least a majority of the implanted dopant to form recesses (124), filling the recesses (124) with SiGe to form embedded source/drain regions (106), and then annealing at 1000-1050 -C by rapid thermal annealing (RTA) for a few seconds or at 1200-1300 -C by laser annealing for a few milliseconds “to activate the implanted dopants in the Si” (1121—23; Figs. 2A—2D). An advantage of annealing after the SiGe deposition “is to reduce the diffusion of PMOS S/D implanted dopants” (124). 1 The Appellants’ Specification states that “[T]he structure in Fig. 5 is produced by performing a thermal process 308 to form source/drain (S/D) extensions 306 conformably surrounding the S/D recess cavities 302. The thermal process 308 can drive out boron at the edges of the boron-doped strained material 304 into the active regions 204 to form S/D extensions 306” (Spec. 120). 3 Appeal 2015-007411 Application 12/984,703 The Examiner apparently relies upon the portion of Brask’s undercut (114) below the edge of the dummy gate (104) as corresponding to the Appellants’ recess cavities and finds that 1) Brask discloses “performing a thermal process (at 750-800-C) to form source/drain (S/D) extensions conformably surrounding the S/D recess cavities (col. 6, lines 4-13 and col. 5, lines 59-62)” (Final Act. 3), and 2) because Wang’s 1200-1300 -C laser annealing temperature (123) overlaps the Appellants’ disclosed about 1150-1250 -C annealing temperature (Spec. 120), “the annealing at 1200-1300-C of Wang necessarily drives out boron from SiGe 120 of Brask to the edge of SiGe 120 and into the active regions to form S/D extensions conformably surrounding the SiGe S/D region 120” (Ans. 2). Establishing a prima facie case of obviousness requires an apparent reason to modify the prior art as proposed by the Examiner. See KSR Int 7 Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). The Examiner does not establish that Brask and Wang would have provided one of ordinary skill in the art with an apparent reason to use the 1200-1300-C temperature of Wang’s annealing, the purpose of which is to activate implanted dopants in Si (123),2 as the temperature used by Brask in selectively depositing epitaxial boron doped Si or SiGe to form source/drain regions (col. 6,11. 1—10). Nor has the Examiner established that Wang’s annealing which, Wang discloses, reduces implanted dopant diffusion (| 24), necessarily would drive the boron dopant in Brask’s SiGe source drain regions (120) (col. 6,11. 1—10) to the edges of those regions and into the surrounding regions. 2 The Examiner’s finding that Wang’s “Si” is shorthand for “SiGe” is unpersuasive due to lacking evidentiary support (Ans. 4). 4 Appeal 2015-007411 Application 12/984,703 Thus, the Examiner has not established a prima facie case of obviousness of the Appellants’ claimed method. DECISION/ORDER The rejections under 35 U.S.C. § 103 of claims 9, 3—17, and 19 over Brask in view of Wang, claims 21—28 over Brask in view of Wang and Matsuo, claims 10—12 over Brask in view of Wang and Cheng and claims 18 and 20 over Brask in view of Wang and Mandelman are reversed. It is ordered that the Examiner’s decision is reversed. REVERSED 5