Ex Parte Chen et alDownload PDFPatent Trial and Appeal BoardNov 9, 201712364105 (P.T.A.B. Nov. 9, 2017) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/364,105 02/02/2009 Nan Chen QC071054 3363 12371 7590 11/14/2017 Mnnrv rre.issle.r Olrk & T owe P P /OT TAT POMM EXAMINER 4000 Legato Road, Suite 310 Fairfax, VA 22033 NGUYEN, VAN THU T ART UNIT PAPER NUMBER 2824 NOTIFICATION DATE DELIVERY MODE 11/14/2017 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): meo.docket@mg-ip.com meo@mg-ip.com ocpat_uspto@qualcomm.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte NAN CHEN, MEHDI HAMIDI SANI, and RITU CHABA Appeal 2017-003649 Application 12/364,105 Technology Center 2800 Before PETER F. KRATZ, ROMULO H. DELMENDO, and JEFFREY T. SMITH, Administrative Patent Judges. KRATZ, Administrative Patent Judge. DECISION ON APPEAL This is a decision on an appeal1 under 35 U.S.C. § 134(a) from the Examiner’s final rejection of claims 1, 4—8, 10-12, 15—20, and 23—28.2 We have jurisdiction pursuant to 35 U.S.C. § 6. Appellants’ invention is directed to a memory device including, inter alia, a memory core array and peripheral logic configured to interface with the memory core array having a footswitch configured to isolate the 1 Appellants identify “QUALCOMM Incorporated” as the real party in interest (App. Br. 3). 2 This is the second appeal involving this Application. In the first appeal (Appeal No. 2013-001904), a PTAB Decision was entered November 24, 2014 reversing a single rejection. Appeal 2017-003649 Application 12/364,105 peripheral logic and a head switch configured to isolate a high voltage supply from the memory core array and a method of reducing leakage current in a memory device. Claim 1 is illustrative and reproduced below: 1. A memory device, comprising: a memory core array including a plurality of bitlines coupled to bit cells; peripheral logic configured to interface with the memory core array; at least one footswitch configured to isolate the peripheral logic; a headswitch configured to isolate a high voltage supply from the memory core array including the bit cells and a sense amplifier during a sleep mode, wherein the headswitch is formed of a plurality of precharge transistors each arranged in series with each of the bit cells coupled to corresponding bitlines and a precharge transistor coupled to the sense amplifier, and used as part of the memory core array; a p-type metal oxide semiconductor (PMOS) transistor configured to isolate the high voltage supply from the sense amplifier during the sleep mode; and an n-type metal oxide semiconductor (NMOS) transistor configured to isolate a low voltage supply from the sense amplifier during the sleep mode. The Examiner relies on the following prior art references as evidence in rejecting the appealed claims: Uchida Arimoto Notani US 5,184,202 US 6,449,204 B1 US 7,345,936 B2 Feb. 2, 1993 Sept. 10, 2002 Mar. 18, 2008 2 Appeal 2017-003649 Application 12/364,105 The Examiner maintains the following grounds of rejection: Claims 1, 4—8, 10-12, 15—20, and 23—28 stand rejected under 35 U.S.C. § 112, first paragraph as failing to comply with the written description requirement. Claims 1, 7, 8, 10-12, 17—20, and 25—28 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Admitted Prior Art (Fig. 1) in view of Uchida and Arimoto. Claims 4—6, 15, 16, 23, and 24 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Admitted Prior Art (Fig. 1) in view of Uchida, Arimoto, and Notani.3 We reverse the stated rejections. Our reasons follow. Written Description Rejection The test for determining compliance with the written description requirement of 35 U.S.C. § 112, first paragraph for later claimed subject matter is whether the disclosure of the application as originally filed reasonably conveys to the artisan that the inventor had possession at that time of the filing of the later claimed subject matter, rather than the presence or absence of literal support in the specification for the claim language. See Vas-Cath Inc. v. Mahurkar, 935 F.2d 1555, 1563—64 (Fed. Cir. 1991) and In reKaslow, 707 F.2d 1366, 1375 (Fed. Cir. 1983). It is the Examiner's burden to establish a prima facie case of non patentability based on the written description requirement by presenting evidence or reasons establishing why persons skilled in the art would not 3 The Examiner mistakenly includes cancelled claims 29 and 32—36 as claims subject to the rejections under 35 U.S.C. § 103(a) (Ans. 3—13; see Final Office Action, Form PTOF 326, Items 5, 7; pp. 4—13; Advisory Action, Form PTOF-303, Item 15; App. Br.; Claims Appendix). 3 Appeal 2017-003649 Application 12/364,105 recognize in the original disclosure a description of the invention defined by the claims. In re Alton, 76 F.3d 1168, 1175 (Fed. Cir. 1996). The Examiner maintains that the appealed claims run afoul of the written description requirement of 35 U.S.C. § 112, first paragraph because (Ans. 2—3; see Final Act. 2—3): It appears that transistor 470 of FIG. 4 is claimed twice in claim 1. First as "at least one footswitch configure[d] to isolate the peripheral logic" on line 4, and later as “an n-type metal oxide semiconductor (NMOS) transistor configured to isolate a low voltage supply from the sense amplifier during the sleep mode” on lines 12-13. Claim 12 recites similar redundancy, such as (1) “isolating, with a footswitch, the peripheral logic from a ground voltage during the sleep mode” on lines 5-6, and “isolating, with an n-type metal oxide semiconductor (NMOS) transistor, a low voltage supply from the sense amplifier” on lines 13-14; (2) "isolating, with a head switch,... a sense amplifier during the sleep mode” on lines 7-8, and “isolating, with a p-type metal oxide semiconductor (PMOS) transistor, a high voltage supply from the sense amplifier" on lines 11-12. Claim 20 recites similar redundancy as in claim 12. The Examiner further states that (Ans. 14)(emphasis added): Appellant argues FIG. 4 of the present invention describes the claimed headswitch comprising PMOS transistors 315 connected to bit lines bit0-bit8 and one PMOS transistor 315 connected to transmission gate 4 coupled to sense amplifier 420. PMOS transistors 315 are configured to isolate a high voltage supply to bit cells and sense amplifier in response to a “precharge” signal, which is in response to a sleep signal slp_ n. Examiner finds this argument persuasive, the 112 rejection regarding the claimed headswitch and p-type metal oxide semiconductor (PMOS) transistor are withdrawn. 4 Appeal 2017-003649 Application 12/364,105 Consequently, the Examiner’s lack of written description rejection as it pertains to the headswitch and PMOS transistor is directed to a portion of the rejection expressly withdrawn by the Examiner (see Ans. 13—14).4 The lack of written description rejection that is maintained by the Examiner pertains to the Examiner’s finding that the footswitch and the n- type metal oxide semiconductor (NMOS) transistor of claim 1 represent a redundancy because “[i]t appears that transistor 470 of FIG. 4 is claimed twice in claim 1” (Ans. 2; see Final Act. 3). Similarly, the Examiner finds the corresponding limitations in independent claims 12 and 20 respecting the footswitch and NMOS transistor represent a redundancy (Ans. 2—3, 13). Appellants contend that written descriptive support is found for the footswitches, e.g. footswitches 305/325 (see Fig. 3) arranged for isolating the peripheral logic, and for an NMOS transistor (470, Fig. 4) arranged for isolating the sense amplifier (420, Fig. 4) during a sleep mode as set forth in paragraph 41 of the Specification, as filed (App. Br. 5—7). The Examiner rejects this argument contending, in rebuttal, that (Ans. 14—15): The specification of the present invention describes, in paragraph [0017], FIG. 4 illustrates a circuit diagram of the ROM of FIG. 3. While FIG. 3 shows footswitches 305 and 325, both connected to peripheral logic 320, FIG. 4 only shows one footswitch (i.e. NMOS transistor 470) connected to the peripheral logic (i.e. sense amplifier) (see annotated FIGS. 3-4 4 The Examiner appears to inadvertently include a section of the expressly withdrawn portion of the lack of written description rejection concerning the headswitch and the PMOS transistor at page 3 of the Answer (see Ans. 13— 14). The expressly withdrawn portion of the lack of written description rejection of claims 1, 4—8, 10-12, 15—20, and 23—28 is not before us for review (Ans. 13). 5 Appeal 2017-003649 Application 12/364,105 of present invention). The 112 rejection regarding the claimed footswitch and n-type metal oxide semiconductor (NMOS) transistor are therefore maintained. Appellants argue that the Examiner’s redundancy basis for the lack of written description rejection for the at least one footswitch and an NMOS transistor lacks merit as it seems to assume that the NMOS transistor and the footswitch are duplicate features and rely on the same disclosure (transistor 470) for support whereas, the Application disclosure, as filed, supports these recited features (footswitch and NMOS transistor) as having differently disclosed and recited functionality and separate support, such as in paragraph 41 of the subject Specification (Reply Br. 2—3;5 App. Br. 5—7). The Examiner does not fully address the argued Specification disclosures and point to any persuasive factual evidence that substantiates or otherwise satisfactorily explain why the described embodiment(s) in the Specification are deficient in descriptive support for the contested claim limitations. In this regard, the Examiner has not established that the Specification specifies the disclosed NMOS transistor 470 as being the only support for the footswitch for the claimed memory device and persuasively explained how the Specification, as filed, requires a footswitch, which the Specification defines as “a transistor positioned between the local ground or low voltage and the system ground or low voltage source (e.g., Vss)” (Spec. 120) as being necessarily limited to an “NMOS transistor configured to isolate a low voltage supply from the sense amplifier during the sleep mode” 5 Our references to the pages of the Reply Brief is based on assigning page numbers in ascending numerical order to the non-paginated pages following page 1 of the Reply Brief. 6 Appeal 2017-003649 Application 12/364,105 to support the Examiner’s lack of descriptive support rejection based on an asserted twice claimed/redundant limitation (claim 1). See Vas-Cath, 935 F.2d at 1562—63 (the written description requirement is a factual question). It follows that the Examiner has not carried the burden of supplying a sufficient factual basis to support a conclusion that the claimed limitations in question fail to find written descriptive support in the disclosure of the application, as originally filed, that reasonably conveys to the artisan that the inventor had possession at that time of the filing of the claimed subject matter. See In re Alton, 76 F.3d at 1175; see also In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992) (“the examiner bears the initial burden, on review of the prior art or on any other ground, of presenting a prima facie case of unpatentability”). Accordingly, the Examiner’s lack of written description rejection is reversed on this appeal record. Obviousness Rejections Concerning the first stated obviousness rejection, the Examiner finds the admitted prior art in Figure 1 discloses or suggests a memory core array, peripheral logic, and at least one footswitch, as required by rejected claim 1 but fails to teach the remaining claim 1 limitations ((Final Act. 4). In addition, the Examiner relies on: (1) Uchida to teach a headswitch configured to isolate a memory core array and a sense amplifier (SA) from a supply voltage (VDD) wherein the headswitch is formed of a plurality of precharge transistors (Q4—Q7) as set forth by the Examiner in the Final Office Action (Final Act. 4; see Ans. 4; Uchida, col. 4,1. 63—col. 5,1. 15; Fig. 1 and 7 Appeal 2017-003649 Application 12/364,105 (2) Arimoto to teach a PMOS transistor (P3) that the Examiner finds to be configured to isolate a high voltage supply (VCCS) from a sense amplifier (SA) during a sleep mode and to teach a NMOS transistor (N3) that the Examiner finds is configured for isolating a low voltage supply (ground voltage) from a sense amplifier (SA) during a sleep mode (Final Act. 5; Ans. 4; Figs. 26, 28). The Examiner maintains that an ordinarily skilled artisan at the time of the invention would have been led to (1) “include a headswitch to the memory of APA as suggested by Uchida in order to increase the speed of reading operation (see col. 3 11. 64-68)” and to (2) switch “off power supply to the sense amplifier during standby mode as suggested by Arimoto to the ROM device of Uchida for purpose of reducing power consumption during a normal operating mode (see col. 10 In. 16)” (Final Act. 5). Moreover, the Examiner notes “that the ROM device of Uchida never enters a twin-cell write mode” as Arimoto describes for the “DRAM device of Arimoto, therefore transistors P4 and N4 of FIG. 26 could be eliminated” (Final Act. 5). The Examiner applies the same prior art in a substantially similar manner to the corresponding features required by independent claims 12 and 20 (Final Act. 6—10). Appellants argue that “the precharge transistors Q4, Q5, Q6, and Q7, as described by Uchida, do not perform isolation of the memory elements Qm or the sense amplifier SA in Fig. 1 of Uchida ‘during a sleep mode,’ as claimed;” rather, Uchida’s transistors Q4— Q7 merely furnish a precharge function while conducting and, when they are not conducting, an evaluation phase is entered as further substantiated by Uchida providing for precharge 8 Appeal 2017-003649 Application 12/364,105 control signals to the precharge transistors, not a sleep mode signal (App. Br. 9; see Uchida col. 5,11. 6—15; Fig. 1). Moreover, Appellants contend that contrary to the Examiner’s findings with respect to Uchida, Uchida fails to teach a headswitch that is configured to isolate a high voltage supply from a memory array, in a manner as required by claim 1, as well as the corresponding limitations as required by independent claims 12 and 20 (App. Br. 10-11). The portions of Uchida relied upon by the Examiner and argued by Appellants appear to support Appellants’ argument that Uchida fails to teach a headswitch configured as required by claim 1 (App. Br. 10; see Uchida, col. 5,11. 6—33; Fig. 1). The Examiner seems to speculate concerning a case when a ROM device of Uchida enters an inactive state of standby/sleep without citation to the disclosure of Uchida for support (Ans. 17). In this regard, the Examiner’s reference to Notani is noted; however, Notani is not relied upon in the first stated obviousness rejection for any purpose (Ans. 17; see Reply Br. 5). The Examiner turns to Arimoto for teachings with respect to certain transistors (PMOS transistor P3 and NMOS transistor N3) that the Examiner finds to be configured for isolating a sense amplifier (SA) from a high voltage supply and a low voltage supply, respectively, during a sleep mode and which transistors the Examiner relies on as corresponding to the PMOS transistor and NMOS transistor required by claim 1 as indicated above, not for a head switch arranged and configured as required by claim 1 (Final Act. 5; Arimoto, Figs. 26, 28). Also, the Examiner does not persuasively articulate how the combined teachings of the applied prior art would have incentivized one of ordinary skill in the art to modify Appellants’ Figure 1 9 Appeal 2017-003649 Application 12/364,105 admitted prior art in a manner to arrive at subject matter corresponding to that claimed. Consequently, the Examiner furnishes insufficient findings of fact and reasoning to support a proposed modification of the APA of Appellants’ Figure 1 based on the cited teachings of Uchida and Arimoto to establish that one of ordinary skill in the art would have been led to modify the APA in a manner that would result in a memory device as required by Appellants’ rejected claim 1 for reasons set forth by Appellants (App. Br. 8—13; Reply Br. 3-5). After all, it is well settled that the burden of establishing a prima facie case of non-patentability resides with the Examiner. See In re Piasecki, 745 F.2d 1468, 1472 (Fed. Cir. 1984). In this regard, “rejections on obviousness grounds cannot be sustained by mere conclusory statements; instead, there must be some articulated reasoning with some rational underpinning to support the legal conclusion of obviousness” being asserted (see App. Br. 10-12; Reply Br. 3-5). In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006) (quoted with approval in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007)). After all, rejections based on § 103(a) must rest on a factual basis with these facts being interpreted without hindsight reconstruction of the invention from the prior art. See In re Warner, 379 F.2d 1011, 1017 (CCPA 1967). For substantially the same reasons, the Examiner has not established that the applied prior art would have led one of ordinary skill in the art to the corresponding subject matter as required by the remaining independent claims, claims 12 and 20, subject to the Examiner’s first stated obvious rejection (App. Br. 10, 11, 13). 10 Appeal 2017-003649 Application 12/364,105 Accordingly, we reverse the Examiner’s first stated obviousness rejection. As for the Examiner’s separately stated obviousness with respect to certain dependent claims, we concur with Appellants that the Examiner has not established that the additionally applied reference, Notani, makes up for all the deficiencies in the base rejection (App. Br. 13—14). It follows that we do not sustain the latter rejection. CONCLUSION The Examiner’s decision to reject the appealed claims is reversed. REVERSED 11 Copy with citationCopy as parenthetical citation