Ex Parte Chen et al

Patent Trial and Appeal Board

Sep 21, 2016

13482029 (P.T.A.B. Sep. 21, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/482,029 05/29/2012
42717 7590 09/23/2016
HA YNES AND BOONE, LLP
IP Section
2323 Victory A venue
Suite 700
Dallas, TX 75219
FIRST NAMED INVENTOR
Chi-Ming Chen
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2010-0954-C I 24061.2179 6974
EXAMINER
SONG, MATTHEW J
ART UNIT PAPER NUMBER
1714
NOTIFICATION DATE DELIVERY MODE
09/23/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ipdocketing@haynesboone.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CHI-MING CHEN, CHUNG-YI YU, CHIA-SHIUNG TSAI,
and HO-YUNG DAVID HWANG
Appeal2015-001644
Application 13/482,029
Technology Center 1700
Before GEORGE C. BEST, JULIA HEANEY, and BRIAND. RANGE,
Administrative Patent Judges.
HEANEY, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 seek our review pursuant to 35 U.S.C. § 134(a) of a
decision of the Examiner to reject claims 1, 3-16, and 18-22 of Application
13/482,029. We have jurisdiction under 35 U.S.C. § 6(b). We affirm.
BACKGROUND
The subject matter on appeal relates to fabrication of a III-V family
compound semiconductor on a silicon substrate in a cluster semiconductor
1 Appellants identify the real party in interest as Taiwan Semiconductor
Manufacturing Co., Ltd. App. Br. 3.
Appeal2015-001644
Application 13/482,029
fabrication tool. Spec. 1. Claim 1, reproduced below from the Claims
Appendix, is illustrative:
1. A method, comprising:
forming a first layer over a silicon wafer, the first layer
containing a group Ill-V compound, wherein the first layer is
formed in a first deposition chamber of a cluster semiconductor
fabrication tool; and
forming a second layer over the first layer, wherein the
second layer contains a dielectric material, and wherein the
second layer is formed in a second deposition chamber of the
cluster semiconductor fabrication tool, and wherein the first and
second deposition chambers are different types of deposition
chambers;
wherein the forming the first layer and the forming the
second layer are performed in a manner such that the wafer is
prevented from being exposed to at least one of oxygen and
silicon between the forming the first layer and the forming the
second layer by transferring the wafer from the first deposition
chamber to the second deposition chamber through a transfer
chamber that interconnects the first and second deposition
chambers, vvherein the transfer chamber is substantially free of
oxygen and silicon during the transferring.
REFERENCES
The Examiner relied upon the following prior art in rejecting the
claims on appeal:
Furukawa
Anderson
Guo
Bour
Haberern
U.S. 5,930,656
U.S. 2004/0077184 Al
U.S. 2006/0154455 Al
U.S. 2007 /0259502 Al
U.S. 2008/0135982 Al
2
Jul. 27, 1999
Apr. 22, 2004
Jul. 13, 2006
Nov. 8, 2007
Jun. 12,2008
Appeal2015-001644
Application 13/482,029
THE REJECTIONS 2
1. Claims 1, 3---6, 9--11, 14--16, and 18-22 are rejected under
35 U.S.C. § 103(a) as unpatentable over the combination of Bour,
Haberern, Anderson, Furukawa.
2. Claims 7, 8, 12, and 13 are rejected under 35 U.S.C. § 103(a) as
unpatentable over the combination of Bour, Haberern, Anderson,
Furukawa, and Guo.
DISCUSSION
Appellants' arguments focus on limitations that appear in claim 1, and
present no argument for separate patentability of any other independent or
dependent claim. App. Br. 14--17; Reply Br. 4--5. Therefore, our decision
on the Examiner's rejection of claim 1 is dispositive of this appeal. See 37
C.F .R. § 41.3 7 ( c )(1 )(iv).
After review of the cited evidence in the appeal record and the
opposing positions of Appellants and the Examiner, we determine that
Appellants have not identified reversible error in the Examiner's rejections.
Accordingly, we affirm the rejections for reasons set forth below, and in the
Examiner's Answer. See Ans. 2-7.
The Examiner finds that Bour teaches a cluster tool that can transfer a
wafer between processing chambers under vacuum or an inert gas, and that
2 The Examiner withdrew all grounds of rejection set forth in the Final
Rejection dated October 8, 2013 and entered new grounds of rejection in the
Answer, based on the same references relied upon in the Final Rejection.
See Ans. 2---6. Appellants elected to file a Reply Brief under 37 C.F.R.
§ 41.41 addressing the new grounds of rejection. Accordingly, our
discussion addresses only the new grounds of rejection entered in the
Answer.
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Appeal2015-001644
Application 13/482,029
Bour, Haberern, and Furukawa teach deposition of a III-V compound layer
in a first chamber followed by deposition of a dielectric layer in a second
chamber. Ans. 6 (citing Bour i-fi-166-74; Haberern i-fi-136-41; Furukawa
1:10-2:15). The Examiner further finds that exposing a substrate to air
during transfer between a III-V deposition chamber and a dielectric
deposition chamber is known to undesirably form an oxide layer (Ans. 7,
(citing Furukawa 1: 10-2: 15) ), and that transferring under a vacuum or inert
gas using a cluster tool is known to prevent oxidation and contamination.
Ans. 6 (citing Anderson i154). The Examiner thus determines that the
method recited in claim 1 would have been obvious to a person of ordinary
skill in the art, in order to prevent undesirable oxide formation or
contamination. Ans. 7.
Appellants present essentially two arguments against the rejection:
( 1) Bour does not explicitly teach that a vacuum environment should be
created between deposition of the first and second layers; and (2) none of the
references, alone or in combination, teach that the transfer envinronment
should be free of silicon, which is undesirable because it acts as a dopant on
the III-V layer. Reply Br. 2--4. Appellants' arguments are not persuasive of
reversible error. Although Bour does not explicitly disclose a vacuum
environment between specific deposition steps, Appellants have not
demonstrated that it would have been beyond the level of ordinary skill in
the art to apply the knowledge of cluster tools using separate deposition
chambers, and transferring between chambers under vacuum or inert gas
using a cluster tool, to include the specific step of applying a vacuum
environment between deposition of the first and second layers. Further,
Appellants' second argument does not persuade us of reversible error in the
Examiner's finding that Anderson i1 54 teaches applying an inert gas in a
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Appeal2015-001644
Application 13/482,029
transfer chamber prevents exposure to sources of contamination of the
substrate. Appellants' argument that "neither Haberern nor Anderson as
cited appear to teach when or in what step should a silicon free environment
be produced" (Reply Br. 4) does not explicitly address Anderson i-f 54, and
further does not show nonobviousness by attacking the references
individually, although the rejection is based on combination of the
references. See In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986)
("Non-obviousness cannot be established by attacking references
individually where the rejection is based upon the teachings of a
combination of references.").
SUMMARY
We affirm the rejections of claims 1, 3---6, 9-11, 14--16, and 18-22 as
unpatentable under 35 U.S.C. § 103(a), for the reasons set forth above.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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