11427495 (P.T.A.B. Feb. 25, 2014)

Ex Parte Chen et al

Patent Trial and Appeal BoardFeb 25, 2014

11427495 (P.T.A.B. Feb. 25, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/427,495 06/29/2006 Xiangdong Chen FIS920060044US1 2528 23389 7590 02/25/2014 SCULLY SCOTT MURPHY & PRESSER, PC 400 GARDEN CITY PLAZA SUITE 300 GARDEN CITY, NY 11530 EXAMINER LAM, CATHY N ART UNIT PAPER NUMBER 2811 MAIL DATE DELIVERY MODE 02/25/2014 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE _________ BEFORE THE PATENT TRIAL AND APPEAL BOARD __________ Ex parte XIANGDONG CHEN, THOMAS W. DYER, KENNETH SETTLEMYER, and HAINING S. YANG __________ Appeal 2011-008843 Application 11/427,495 Technology Center 2800 ___________ Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and JAMES C. HOUSEL, Administrative Patent Judges. HANLON, Administrative Patent Judge. DECISION ON APPEAL Appeal Applica A T decision also pen under 3 W T Appella accordin 1 Spec., 2011-0088 tion 11/42 . STAT he Appell finally re ding but h 5 U.S.C. § e REVER he subject nts’ FIG. 5 g to one e A comprisi in a paras. [00 43 7,495 EMENT ants filed a jecting cla ave been w 6(b). SE. matter on , reproduc mbodimen ppellants’ ng semico portion of gate dielec 48] and [0 OF THE C n appeal u ims 1, 9-1 ithdrawn appeal is ed below, t of the di FIG. 5 dep nductor de semicond tric layer 049]. 2 ASE nder 35 U 1, 19, and from cons directed to illustrates sclosed in icts a sem vice struc uctor devi 22, and str .S.C. § 13 31-40. Cl ideration. a semicon a semicon vention. S iconducto ture 14, a ce structur essor laye 4 from an aims 17 an We have ductor de ductor de pec., para r device channel lo e 14 under rs 30.1 Examiner d 26-30 a jurisdictio vice. The vice . [0030]. cated ’s re n Appeal 2011-008843 Application 11/427,495 3 Claim 1 is representative of the subject matter on appeal and is reproduced below from the Claims Appendix of the Appeal Brief dated August 30, 2010. The limitations at issue have been italicized. 1. A semiconductor device comprising: a p-type field effect transistor (FET) having a channel region located in a semiconductor device structure, said semiconductor device structure having a top surface that is oriented along one of a first set of equivalent crystal planes and one or more additional surfaces that are oriented along a second, different set of equivalent crystal planes, said one or more additional surfaces form acute angles with the top surface of the semiconductor device structure; and one or more stressor layers adjacent to the channel region of the p-type FET and adjacent to said one or more additional surfaces of the semiconductor device structure, said one or more stressor layers are arranged and constructed to apply compressive stress to the channel region of the p-type FET, and have a lattice constant smaller than that of the semiconductor device structure, wherein a tensile stress is created in the stressor layers. The claims on appeal stand rejected as follows: (1) claims 1, 9, 11, 19, and 31-40 under 35 U.S.C. § 103(a) as unpatentable over Shimamune2 in view of Lin;3 and (2) claim 10 under 35 U.S.C. § 103(a) as unpatentable over Shimamune in view of Lin, and further in view of Awano.4 B. DISCUSSION Referring to Shimamune FIG. 4F, reproduced below, the Examiner finds Shimamune discloses a semiconductor device comprising a p-type field effect 2 US 2006/0138398 A1, published June 29, 2006. 3 US 2006/0081875 A1, published April 20, 2006. 4 US 2003/0094637 A1, published May 22, 2003. Appeal Applica transisto The Exa one or m the sem also com adjacen structur construc T and 14B wherein 4. Rath constan compre N 218 whi wherein 5 Exami 2011-0088 tion 11/42 r having c miner find ore additi iconductor prises str t to one or e. The Ex ted to app Sh he Examin have a la a tensile s er, Shimam t than the s ssive stres onetheles ch have a a tensile s ner’s Answ 43 7,495 hannel reg s the sem onal surfa device str essor layer more addi aminer fin ly compre imamune F er finds S ttice const tress is cr une discl emicondu sors. See, s, the Exam lattice con tress is cr er dated ion 11G l iconductor ces 14c th ucture. T s 14A and tional surf ds stressor ssive stres IG. 4F de himamune ant smalle eated in th oses that t ctor devic e.g., Shim iner finds stant smal eated in th December 4 ocated in a device str at form acu he Examin 14B adja aces 14c o layers 14 s to chann picts a sem does not r than the e stressor he stressor e structure amune, pa Lin disclo ler than th e stressor 1, 2010. semicond ucture has te angles er finds th cent to cha f the semi A and 14B el region 1 iconducto disclose th semicondu layers as r layers hav , i.e., stres ras. [0011 ses one o e semicon layers. An uctor dev top surfa with top s e semicon nnel regio conductor are arran 1G. Ans. r device. at stressor ctor devic ecited in c e a larger sor layers ], [0038], r more stre ductor dev s. 4. The ice structu ce 14b and urface 14b ductor dev n 11G and device ged and 3-4.5 layers 14A e structure laim 1. Id lattice are SiGe [0077]. ssor layer ice structu Examiner re. of ice , . at s re, Appeal 2011-008843 Application 11/427,495 5 concludes it would have been obvious to one of ordinary skill in the art to replace the compressive stressors disclosed in Shimamune with the tensile stressors disclosed in Lin. Id. Referring to paragraph [0015] of their Specification, the Appellants explain the claimed invention as follows: Appellants disclose that the Si:C stressor layers contain an intrinsic tensile stress due to lattice mismatch between Si:C and Si, which is contained by the semiconductor device structure, wherein when the one or more additional surfaces of the semiconductor device structure form acute angles with the top surface of the device, the stressor layers apply a compressive stress to the channel region of the pFET. Si:C stressor layers have a lattice constant smaller than that of a semiconductor device structure. That is, Appellants utilize angled surfaces, and materials having an intrinsic tensile stress, to induce the opposite stress, i.e., compressive stress, in the channel region of the device. App. Br. 7 (italics added). The Appellants argue that Shimamune, on the other hand, “relies upon stressor layers having an intrinsic compressive stress to produce a compressive stress in the channel region of the device.” Id. at 9. The Appellants argue: [B]ecause Shimamune et al. relies upon a SiGe stressor layer, i.e., stressor layers having a greater lattice constant than the substrate on which they are formed, having an intrinsic compressive stress to induce a compressive stress in the channel region of a p-type device, Shimamune et al. leads away from a structure in which stressor layers having an intrinsic tensile stress produce a compressive stress in the channel region of a p-type device, as required by Appellants’ claims. Id. at 8-9 (italics added). The Appellants elaborate on this argument in the Reply Brief: One of ordinary skill in the art would conclude that a modification to Shimamune et al. to include a stressor layer with a Appeal 2011-008843 Application 11/427,495 6 lattice constant that is less than the lattice constant of the semiconductor device would produce a stressor layer having an internal tensile[ stress]. Therefore, because Shimamune et al. discloses inducing the same stress type on the channel region that is formed in the stressor layer, Shimamune et al. leads away from stressor layers having a lattice constant that is less than the lattice constant of the semiconductor device, because the stressor layer with the smaller lattice constant will have an internal tensile stress that will induce a tensile stress to the device channel. Reply Br. 4-5 (emphasis added).6 Significantly, the Examiner has failed to establish that the proposed modification of Shimamune would have resulted in the claimed invention. The portion of Lin relied on by the Examiner (i.e., para. [0049]) discloses that “the material in the third region 220[7] may experience tensile or compressive strain from a multiplicity of materials and from a multiplicity of abutting regions.” The Examiner does not explain, in any detail, why this disclosure in Lin would have led one of ordinary skill in the art to expect that replacing compressive stressors 14A and 14B in Shimamune with the tensile stressors in Lin would have resulted in the application of compressive stress to Shimamune’s channel region 11G as recited in claim 1. For this reason, the § 103(a) rejection of claims 1, 9, 11, 19, and 31-40 is not sustained. The Examiner does not rely on Awano to teach the stressor layer(s) recited in claim 1. Rather, the Examiner relies on Awano to teach the semiconductor-on- insulator (SOI) structure recited in claim 10. Ans. 8-9, 12. Therefore, the § 103(a) rejection of claim 10 is not sustained. 6 Reply Brief dated February 1, 2011. 7 Paragraph [0033] of Lin discloses that the third region 220 abuts the underlying substrate 202 and occupies the channel region 212. Appeal 2011-008843 Application 11/427,495 7 C. DECISION The decision of the Examiner is reversed. REVERSED bar