Ex Parte Chen et al

Board of Patent Appeals and Interferences

Mar 1, 2010

11362072 (B.P.A.I. Mar. 1, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte DEVEREAUX C. CHEN and JEFFREY R. ZIMMER

____________

Appeal 2008-005671
Application 11/362,0721
Technology Center 2100
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Decided: March 1, 2010
____________

Before JAMES D. THOMAS, JOHN A. JEFFERY, and
CAROLYN D. THOMAS, Administrative Patent Judges.

C. THOMAS, Administrative Patent Judge.

DECISION ON APPEAL

1 Application filed February 27, 2006. The real party in interest is Juniper
Networks, Inc.
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I. STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection
of claims 1, 3, 11-17, and 19, which are all the claims under appeal in the
application, as claims 5-7, 9, and 10 are allowed, claims 2 and 4 are objected
to, and claim 8 is cancelled. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

A. INVENTION
Appellants invented a system for providing a queue including a first
queuing area configured to enqueue and dequeue data. A second queuing
area receives data from the first queuing area when the first queuing area has
data available to be dequeued. Bypass logic is coupled to the buffer. The
bypass logic causes the data to bypass the first queuing area and to go
straight to the second queuing area when the second queuing area is ready to
receive data and the first queuing area is empty. (Spec., ¶[0009].)

B. ILLUSTRATIVE CLAIM
The appeal contains claims 1, 3, 11-17, and 19. Claims 1, 11, and 17
are independent claims. Claim 1 is illustrative:
1. A queue comprising:
a first queue configured to enqueue and dequeue data
units, the first queue including a plurality of parallel sub-queues that
queue a plurality of parallel data units;
a second queue configured to receive data units from the
first queue when the first queue has data units available to be
dequeued, the second queue including a first buffer configured to
store a first set of the parallel data units and a second buffer, having a
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lower output priority than the first buffer, configured to store a second
set of the parallel data units; and
bypass logic coupled to the second queue, the bypass
logic configured to bypass the first queue and to forward data to the
second queue when the second queue is ready to receive data and the
first queue is empty.

C. REFERENCES
The references relied upon by the Examiner as evidence in rejecting
the claims on appeal are as follows:
Parks US 5,517,671 May 14, 1996
Umeki US 5,928,354 Jul. 27, 1999
Bronson US 6,065,088 May 16, 2000

D. REJECTIONS
The Examiner entered the following rejections which are before us for
review:
(1) Claims 11-16 are rejected under 35 U.S.C. § 103(a) as being
unpatentable over Parks, Bronson and Umeki; and
(2) Claims 1, 3, 17, and 19 are rejected under 35 U.S.C. § 103(a) as
being unpatentable over Bronson and Umeki.

II. FINDINGS OF FACT
The following findings of fact (FF) are supported by a preponderance
of the evidence.
Bronson
1. Bronson discloses that “there exists an incoming command queue
and three outgoing command queues.” (Col. 5, ll. 8-9.)
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2. Bronson discloses “a three deep processor read queue and a four
deep I/O read queue.” (Col. 5, ll. 21-23.)
3. In Bronson’s Fig. 2, “[t]wo interrupt queues 104, 106 are provided,
one for each possible processor served by controller chip 103. A queue
element 104, 106, 108, 110 contains the information associated with an
incoming interrupt.” (Col. 6, l. 19-24.)
4. Bronson discloses that “an interrupt router and I/O command
queuing system and method . . . enforces strict ordering of EOI commands
relative to MMIO accesses while simultaneously allowing INR and IRR
commands to bypass enqueued MMIO accesses.” (Col. 8, ll. 10-15.)
5. In Bronson, “[a] queue element 104, 108 is marked full when it is
updated with an interrupt. A queue element 104, 108 is marked empty (not
full) when the interrupt contained in that queue element is taken by
processor 80.” (Col. 6, ll. 38-41.)
6. In Bronson, “[t]here are two interrupt queue multiplexers 120, 122
one for each possible processor served by controller chip 103. Each
multiplexer 120, 122 has three inputs 117/103/105 and 107, 109, 119,
respectively.” (Col. 7, ll. 16-19.)
7. Bronson discloses that “[w]ith respect to MUX 120, two of the
inputs to come [sic] from interrupt queue 104 on lines 103 and 105.” (Col.
7, ll. 28-29.)
Umeki
8. Umeki discloses “[w]hen the instruction queue buffer 2 is empty
and the instruction queue buffer 2 is skipped . . . , the CPU1 fetches the
instruction code directly from the high-speed memory 3a by skipping the
instruction queue buffer 2.” (Col. 4, ll. 32-36.)
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Parks
9. Parks discloses that “[t]he system bus 14 supports all
communications between processors, memories, and I/O channels in the
computer system.” (Col. 4, ll. 7-9.)
10. Parks discloses that “[t]he system controller 20 enables the input
of data to the system bus 14 through the use of interrupts.” (Col. 4, ll. 63-
64.)

III. PRINCIPLES OF LAW
“What matters is the objective reach of the claim. If the claim extends
to what is obvious, it is invalid under § 103.” KSR Int’l Co. v. Teleflex, Inc.,
550 U.S. 398, 419 (2007). To be nonobvious, an improvement must be
“more than the predictable use of prior art elements according to their
established functions.” Id. at 417.
The Examiner bears the initial burden of presenting a prima facie case
of obviousness, and Appellants have the burden of presenting a rebuttal to
the prima facie case. In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992).
Appellants have the burden on appeal to the Board to demonstrate error in
the Examiner’s position. In re Kahn, 441 F.3d. 977, 985-986 (Fed. Cir.
2006).

IV. ANALYSIS
Grouping of Claims
In the Appeal Brief, Appellants argue claims 1 and 3 as a group (App.
Br. 5-9). For claim 3, Appellants repeat the same argument made for claim
1. We will, therefore, treat claim 3 as standing or falling with claim 1.
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Appellants argue claims 17 and 19 as a group (App. Br. 11-13). For
claim 19, Appellants repeat the same argument made for claim 17. We will,
therefore, treat claim 19 as standing or falling with claim 17.
Appellants argue claims 11-16 as a group (App. Br. 14-16). For claim
12-16, Appellants repeat the same argument made for claim 11. We will,
therefore, treat claim 11-16 as standing or falling with claim 11. See 37
C.F.R. § 41.37(c)(1)(vii). See also In re Young, 927 F.2d 588, 590 (Fed. Cir.
1991).

The Obviousness Rejection
We now consider the Examiner’s rejection of the claims under
35 U.S.C. § 103(a).
Claims 1 and 3
Appellants contend that “[q]ueues 134 and 136 of Bronson, therefore,
are separate and independent command queues. Simply because Bronson
describes both of these queues as being within interrupt router 142 does not
make these queues ‘parallel sub-queues that queue a plurality of parallel data
units,’ as recited in claim 1.” (App. Br. 7.) Appellants further contend that:
“[q]ueues 148 and 150 are two distinct and independent queues,
not buffers of a single queue. Additionally, queues 148 and 150
do not store sets of parallel data units, instead, the data in
queues 148 and 150 appear to progress through queues 148 and
150 in a non-parallel manner in which queue 150 is given
higher priority.”

(App. Br. 8.) Appellants contend that “one of ordinary skill in the art
reading Umeki would not be motivated to bypass interrupt router 142 of
Bronson in the manner suggested by the Examiner.” (App. Br. 9.)
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The Examiner found that in Bronson “[t]he first queue 142 includes a
plurality of parallel sub-queues that queue a plurality of parallel data units
(EOI queue 136 and INR, IRR queue 134, Figure 3). These queues are
parallel since the data in these queues progress through parallel paths
through the system of Figure 3.” (Ans. 10-11.)

Issue: Have Appellants shown that the Examiner erred in finding that
the combination of Bronson and Umeki discloses the first queue including a
plurality of parallel sub-queues that queue a plurality of parallel data units
and that there is proper motivation for using a bypass logic in the system of
Bronson?

In Bronson’s system for interrupt command queuing and ordering,
Bronson discloses a plurality of command queues consisting of sub-queues
(FF 1-2). Bronson further discloses that the queues are provided for each
possible processor (FF 3). In essence, Appellants contend that Bronson’s
queues are distinct and independent and thus cannot include parallel sub-
queues. We disagree.
As noted by the Examiner, Appellant has not provided any special
definition for the claimed “parallel sub-queues” (Ans. 11). The ordinary and
usual meaning of “parallel” is an arrangement or state that permits several
operations or tasks to be performed simultaneously rather than
consecutively. Merriam-Webster’s Collegiate Dictionary 842 (10th ed.
1997). Bronson discloses simultaneous processing (FF 4). Bronson further
discloses that the queues are provided for each possible processor (FF 3),
which suggest multiple processors, and hence parallel processing within the
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system. Furthermore, Appellants have not established that having distinct
and independent queues necessarily negates parallelism.
As for the bypass logic (e.g., skipping step) disclosed by Umeki
(FF 8), Appellants contend that one of ordinary skill in the art would not
have been motivated to use such a bypass logic in the system of Bronson
(App. Br. 9). We disagree.
Umeki discloses a bypass logic that bypasses the instruction queue
when it is empty (FF 8). Similarly, Bronson discloses marking a queue
element as empty (FF 5). Thus, we find that the claimed “bypass logic
configured to bypass the first queue and to forward data to the second queue
. . . and the first queue is empty” reads on Umeki’s queue skipping function
and Umeki’s/Bronson’s empty queue detection (emphasis added).
Furthermore, the Examiner found that “[s]ince the routing unit of Bronson is
made up of queues, one would be motivated to bypass [an empty queue] as
taught by Umeki [for the purpose of improving speed].” (Ans. 13.)
The Supreme Court has held that in analyzing the obviousness of
combining elements, a court need not find specific teachings, but rather may
consider “the background knowledge possessed by a person having ordinary
skill in the art” and “the inferences and creative steps that a person of
ordinary skill in the art would employ.” See KSR, 550 U.S. at 418. To be
nonobvious, an improvement must be “more than the predictable use of prior
art elements according to their established functions,” id. at 417, and the
basis for an obviousness rejection must include an “articulated reasoning
with some rational underpinning to support the legal conclusion of
obviousness.” Id.
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Here, the Examiner has found actual teachings in the prior art and has
provided a rationale for the combination. Further, the teachings suggest that
the combination involves the predictable use of prior art elements according
to their established functions. Accordingly, we find that the Examiner has
provided sufficient motivation for modifying Bronson with the teachings of
Umeki.
Thus, Appellants have not persuaded us of error in the Examiner’s
conclusion of obviousness for representative claim 1. Therefore, we affirm
the Examiner’s § 103 rejection of independent claim 1 and of claim 3, which
falls therewith.

Claims 17 and 19
Appellants contend that “[t]he fact that a multiplexer can be used to
‘select signals’ in no way discloses or suggests the multiplexer of clam 17,
which ‘has a plurality of inputs connected to different stages of the queue.’”
(App. Br. 12.)
The Examiner found that “multiplexers are shown to be used in the
selection of signals as in Figure 3, reference #144 and such a component
would be useful in selecting signals from either bus 149 or bus 151 (Figure
3). (Ans. 14.)

Issue: Have Appellants shown that the Examiner erred in finding that
the combination of Bronson and Umeki discloses a multiplexer having a
plurality of inputs connected to different stages of the queue?

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Bronson discloses using a multiplexer having three inputs, two of
such inputs coming from the interrupt queues (FF 6-7). In other words,
Bronson discloses a multiplexer having a plurality of inputs connected to
different stages of the queue. Therefore, we find that the claimed
multiplexer reads on Bronson’s multiplexer configuration.
Thus, Appellants have not persuaded us of error in the Examiner’s
conclusion of obviousness for representative claim 17. Therefore, we affirm
the Examiner’s § 103 rejection of independent claim 17 and of claim 19,
which falls therewith.

Claims 11-16
Appellants contend that “[a]lthough Parks discloses two processors 16
and 18, these processors appear to be standard processors in a personal
computer system. Processors 16 and 18 of Parks, however, are not disclosed
or suggested as being configured to receive memory requests from a request
manager.” (App. Br. 14) (citation omitted.)
The Examiner found that “controller 20 enables the input of data to
the system bus 14 and the system bus supports communication to the
processors. Therefore, the processors do receive data from the controller
20.” (Ans. 15) (citations omitted.)

Issue: Have Appellants shown that the Examiner erred in finding that
the combination of Parks, Bronson, and Umeki discloses a plurality of
parallel processors configured to receive the memory requests from the
request manager?”

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As noted supra, Bronson discloses multiple processors and
simultaneous processing which suggests a plurality of parallel processors.
Parks also discloses using multiple processors (FF 9). The Examiner found
that Parks further disclose processors configured to receive memory requests
from a request manager (Ans. 15). We agree.
For example, Parks discloses communications between processors and
memories (FF 9) and a system controller for enabling the communication
(FF 10). Thus, Parks’ system controller (e.g., request manager) enables the
input of data to the system bus/processors.
“[A]nalysis [of whether the subject matter of a claim would have been
obvious] need not seek out precise teachings directed to the specific subject
matter of the challenged claim, for a court can take account of the inferences
and creative steps that a person of ordinary skill in the art would employ.”
KSR, 550 U.S. 398 at 418 (quoting In re Kahn, 441 F.3d at 988); see also
DyStar Textilfarben GmbH & Co. Deutschland KG v. C.H. Patrick Co., 464
F.3d 1356, 1361 (“The motivation need not be found in the references
sought to be combined, but may be found in any number of sources,
including common knowledge, the prior art as a whole, or the nature of the
problem itself.”); In re Bozek, 416 F.2d 1385, 1390 (CCPA 1969) (“Having
established that this knowledge was in the art, the examiner could then
properly rely, as put forth by the solicitor, on a conclusion of obviousness
‘from common knowledge and common sense of the person of ordinary skill
in the art without any specific hint or suggestion in a particular reference.”’);
In re Hoeschele, 406 F.2d 1403, 1406-07 (CCPA 1969) (“[I]t is proper to
take into account not only specific teachings of the references but also the
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inferences which one skilled in the art would reasonably be expected to draw
therefrom”) (internal citations omitted).
Here, the Examiner has established that it is known to have processors
configured to receive requests from a system controller. Thus, the Examiner
has shown that common sense dictates that processors could be configured
to receive memory requests from a request manager.
Thus, Appellants have not persuaded us of error in the Examiner’s
conclusion of obviousness for representative claim 11. Therefore, we affirm
the Examiner’s § 103 rejection of independent claim 11 and of claims 12-16,
which fall therewith.

V. CONCLUSIONS
We conclude that Appellants have not shown that the Examiner erred
in rejecting claims 1, 3, 11-17, and 19.
Thus, claims 1, 3, 11-17, and 19 are not patentable over the cited prior
art.

VI. DECISION
In view of the foregoing discussion, we affirm the Examiner’s
rejection of claims 1, 3, 11-17, and 19.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv) (2009).

AFFIRMED
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