Ex Parte Chee et alDownload PDFPatent Trial and Appeal BoardSep 19, 201311413439 (P.T.A.B. Sep. 19, 2013) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/413,439 04/28/2006 Tay Liang Chee MI22-3053 9640 21567 7590 09/20/2013 Wells St. John P.S. 601 West First Avenue Suite 1300 Spokane, WA 99201-3828 EXAMINER CRUZ, LESLIE PILAR ART UNIT PAPER NUMBER 2826 MAIL DATE DELIVERY MODE 09/20/2013 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte TAY LIANG CHEE, TAN KOK CHUA, and LEOW SEE HIONG ___________ Appeal 2011-001527 Application 11/413,439 Technology Center 2800 ____________ Before CARL W. WHITEHEAD, JR., ERIC S. FRAHM, and ANDREW J. DILLON, Administrative Patent Judges. WHITEHEAD, JR., Administrative Patent Judge. DECISION ON APPEAL Appeal 2011-001527 Application 11/413,439 2 STATEMENT OF THE CASE Appellants are appealing claims 1-5, 7-9, 16-24, 33, 38, 44, and 47. Appeal Brief 3. We have jurisdiction under 35 U.S.C. § 6(b) (2012). We affirm. Introduction The invention is directed to a semiconductor stacked die package wherein the stacked die package consists of a base substrate, a pair of flip chip stacks, electrically conductive interconnect wires, and an electrically insulative encapsulant. Appeal Brief 4. Illustrative Claim 1. A stacked die package consisting of: a base substrate; two pairs of flip chip stacks, each pair having a flip chip in die up orientation, a flip chip in die down orientation and an insulative printed circuit board interposer substrate to which the die up and die down flip chips electrically connect; a first of the two pairs of flip chip stacks adhesively bonded to the base substrate; a second of the two pairs of flip chip stacks adhesively bonded to the first pair of flip chip stacks by an insulative adhesive; electrically conductive interconnect wires electrically connecting the interposer substrates of the first and second stacks with the base substrate; and an electrically insulative encapsulant received directly over the second stack, between the interposer substrates of the first and second stacks, and between the interposer substrate of the first stack and the base substrate. Appeal 2011-001527 Application 11/413,439 3 Rejections on Appeal Claims 1-5, 7, 8, 16-22, 24, 44, and 47 stand rejected under 35 U.S.C. §103(a) as being unpatentable over Kurita (U.S. Patent Application Publication Number 2006/0063312 A1; published March 23, 2006) and Miyata (U.S. Patent Application Publication Number 2002/0180025 A1; published December 5, 2002). Answer 3-19. Claims 33 and 38 stand rejected under 35 U.S.C. §103(a) as being unpatentable over Maeda (U.S. Patent Application Publication Number 2003/0178716 A1; published September 25, 2003) and Miyata. Answer 19-22. Claims 9 and 23 stand rejected under 35 U.S.C. §103(a) as being unpatentable over Kurita, Miyata, and St. Amand (U.S. Patent Number 6,930,378 B1; issed August 16, 2005). Answer 22-23. Issue Does Kurita or Miyata, either alone or in combination teach or suggest a semiconductor stacked die package wherein the stacked die consists of a base substrate, a pair of flip chip stacks, electrically conductive interconnect wires, and an electrically insulative encapsulant as recited in claim 1? ANALYSIS We have reviewed the Examiner’s rejections in light of Appellants’ arguments that the Examiner has erred. We disagree with Appellants’ conclusions. We concur with the findings and reasons set forth by the Examiner in the action from which this appeal is taken and the reasons set forth by the Examiner in the Answer in response to Appellants’ Appeal Appeal 2011-001527 Application 11/413,439 4 Brief. However, we highlight and address specific findings and arguments for emphasis as follows. Appellants argue Kurita does not disclose or suggest the claimed interposer substrates or the recited encapsulant directly over the second stack. Appeal Brief 14. However, Kurita discloses an interposer substrate (103, 105, and 107) electrically insulative encapsulant (119, 125, 127, and 135). See Kurita, Figures 20A and 20B; see also Answer 3. Appellants further argue that the combination of Kurita and Miyata does not suggest the claimed flip chip stacked configuration including the encapsulant and interposer. Appeal Brief 15. We do not find Appellants’ argument to be persuasive. In particular, we observe that Appellants address the cited references in isolation. Appeal Brief 14. Appellants’ arguments do not take into account what the collective teachings of the prior art would have suggested to one of ordinary skill in the art and are therefore ineffective to rebut the Examiner’s prima facie case of obviousness. See In re Keller, 642 F.2d 413, 425 (CCPA 1981)(“The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art.” (Emphasis added) (citations omitted)). We agree with the Examiner’s findings that the combination of Kurita and Miyata discloses a semiconductor package having stacked flip chips, an interposer and encapsulant. See Answer 3-19. Appeal 2011-001527 Application 11/413,439 5 “Common sense teaches, however, that familiar items may have obvious uses beyond their primary purposes, and in many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 420 (2007). The claimed invention stack well known flip chip dies employing an interposer, encapsulant and electrically conductive means. See claim 1. The claimed invention components are well known in the technology and constructing them into a single package does not signify anything novel or new and as such, the claimed configuration is well within the purview of an artisan skilled in the art. Therefore, we sustain the Examiner obviousness rejections of claim 1 for the reasons stated above. Further, Appellants contend that all of the independent claims, as well as, the dependent claims are allowable for the same reasons as claim 1 is allowable (Appeal Brief 16- 18), however since we do not find that the Examiner erred in rejecting claim 1, we sustain the obviousness rejections of claims 2-5, 7-9, 16-24, 33, 38, 44, and 47 for the same reasons stated above. DECISION The Examiner’s 35 U.S.C. §103 rejections of claims 1-5, 7-9, 16-24, 33, 38, 44, and 47 are affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See 37 C.F.R. § 41.50(f). AFFIRMED llw Copy with citationCopy as parenthetical citation