Ex Parte Chauvel

Board of Patent Appeals and Interferences

May 29, 2009

11188336 (B.P.A.I. May. 29, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte GERARD CHAUVEL
____________

Appeal 2008-004899
Application 11/188,336
Technology Center 2100
____________

Decided1: May 29, 2009
____________

Before HOWARD B. BLANKENSHIP, JAY P. LUCAS, and
JOHN A. JEFFERY, Administrative Patent Judges.

BLANKENSHIP, Administrative Patent Judge.

DECISION ON APPEAL

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
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Application 11/188,336

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STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1-19, which are all the claims in the application. We
have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

Invention
Appellant’s invention relates to a processor, system, and method to
disable a wide prefix (title). The method selectively disables an ability of an
opcode of a first instruction set to act as a prefix for other opcodes in the
first instruction set (Fig. 5; Spec. ¶¶ [0034]-[0035]).
The system includes instruction fetch logic configured to fetch a
stream of opcodes (Fig. 2, element 154; Spec. ¶ [0022]). A decode logic is
coupled to the instruction fetch logic (Fig. 2, element 152; Spec. ¶ [0022]).
A wide enable flag is coupled to the decode logic (Fig. 3, element 198; Spec.
¶ [0026]). The decode logic decodes the opcode as a wide prefix in a first
instruction set if the wide enable flag is asserted (Spec. ¶ [0027]), and
decodes the opcode as other than a wide prefix in the first instruction set if
the wide enable flag is not asserted (Spec. ¶ [0027]).

Representative Claim
6. A processor comprising:
an instruction fetch logic configured to fetch a stream of
opcodes from memory;
a decode logic coupled to the instruction fetch logic; and
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a WlDE enable flag, the WlDE enable flag coupled to the
decode logic;
wherein the decode logic is configured to decode an opcode as
a WlDE prefix in a first instruction set if the WlDE enable flag is
asserted, and wherein the decode logic is configured to decode the
opcode as other than a WlDE prefix in the first instruction set if the
WlDE enable flag is not asserted.

Prior Art
Petrick 5,892,966 Apr. 6, 1999
Grieb 6,205,540 B1 Mar. 20, 2001
Gorishek 6,480,952 B2 Nov. 12, 2002

Tim Lindholm, et al., The JavaTM Virtual Machine Specification, 360
(identified by the Examiner as pages 1 and 2) (Prentice Hall, 2nd ed. 1999),
available at
http://java.sun.com/docs/books/jvms/second_edition/html/Instructions2.doc1
5.html#wide.

Examiner’s Rejections
Claims 1-14, 18, and 19 stand rejected under 35 U.S.C. §103(a) as
being unpatentable over the Java Virtual Machine Specification and Grieb.
Claims 15 and 16 stand rejected under 35 U.S.C. §103(a) as being
unpatentable over the Java Virtual Machine Specification, Grieb, and
Gorishek.
Claim 17 stands rejected under 35 U.S.C. §103(a) as being
unpatentable over the Java Virtual Machine Specification, Grieb, Gorishek,
and Petrick.
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Claim Groupings
Based on Appellant’s arguments in the Appeal Brief, we will decide
the appeal on the basis of claim 6. See 37 C.F.R. § 41.37(c)(1)(vii).

ISSUE
Would a person of ordinary skill in the art at the time of invention
have been able to increase the number of functions associated with the wide
opcode disclosed in the Java Virtual Machine Specification using an opcode
resolving flag as disclosed in Grieb, for the benefit of allowing the number
of opcode functions to exceed the number of available opcodes as taught by
Grieb?

FINDINGS OF FACT
Grieb
1. Grieb discloses an instruction fetch logic configured to fetch a
stream of opcodes from memory (Fig. 2, bus control 112 in processor 110;
col. 4, ll. 60-67; col. 7, l. 67 to col. 8, l. 4).
2. Decode logic is coupled to the instruction fetch logic (Fig. 2,
instruction decode unit 122; col. 4, l. 66).
3. An opcode resolving flag (or K flag) is coupled to the decode
logic (Fig. 2, flag K in element 130; col. 5, ll. 4-8; col. 7, l. 61-65).
4. The opcode resolving flag allows an opcode to be associated
with multiple functions. An opcode is associated with a “setting” function
when the resolving flag is set. The same opcode is associated with a
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“clearing” function when the resolving flag is cleared (col. 7, l. 60 to col. 8,
l. 48; e.g., Fig. 3, 0xB0 opcode can be a branch instruction or a stack
instruction).
5. A person of ordinary skill in the art, after reading Grieb, would
recognize that the opcode resolving flag allows the number of opcode
functions to exceed the number of available opcodes (Abstract; col. 2, ll. 60-
62).
Java Virtual Machine Specification
6. A wide opcode is an instruction that modifies the behavior of
another instruction. The wide opcode is followed in the compiled code by
the opcode of the instruction wide modifies. Two unsigned bytes follow the
modified opcode and are assembled into a 16-bit unsigned index (pp. 1-2).

PRINCIPLES OF LAW
Claim Interpretation
During examination, claims are to be given their broadest reasonable
interpretation consistent with the specification, and the language should be
read in light of the specification as it would be interpreted by one of ordinary
skill in the art. In re Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1364 (Fed.
Cir. 2004) (citations omitted). The Office must apply the broadest
reasonable meaning to the claim language, taking into account any
definitions presented in the specification. Id. (citing In re Bass, 314 F.3d
575, 577 (Fed. Cir. 2002)).

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Obviousness
The question of obviousness is resolved on the basis of underlying
factual determinations including (1) the scope and content of the prior art,
(2) any differences between the claimed subject matter and the prior art, and
(3) the level of skill in the art. Graham v. John Deere Co., 383 U.S. 1, 17
(1966).
The combination of familiar elements according to known methods is
likely to be obvious when it does no more than yield predictable results.
KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 416 (2007).

ANALYSIS
Section 103 rejection of claims 1-14 and 18-19
Appellant argues claim 6 as the representative claim of this group.2
Grieb discloses the limitations of claim 6 (FF 1-4) except for the
opcode being “WIDE.” The Java Virtual Machine Specification describes
the wide opcode (FF 6). A person of ordinary skill in the art at the time of
invention would have used a resolving flag as taught by Grieb to associate
an opcode with a wide function when the resolving flag is set, and to
associate the opcode with another function when the resolving flag is
cleared, for the benefit of allowing the number of opcode functions to
exceed the number of available opcodes as taught by Grieb (FF 4 and FF 5).
Appellant argues that the wide prefix is decoded but not executed, and
next alleges that the references do not teach or suggest “a system where one

2 Claim 1 seems to be of much broader scope than claim 6.
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of two possible states of an opcode is not executed” (Br. 12). However, “a
system where one of two possible states of an opcode is not executed” is not
recited in claim 6, and Appellant has not provided a sufficient basis for
reading this recitation into claim 6.
Appellant has also provided no evidence to support the allegation that
the wide opcode is not executed, other than a statement from Appellant’s
“Background of the Invention” section of the Specification (at 1). This
section states that “the processor decodes the WIDE but does not execute a
‘WIDE’ function; rather, the processor adjusts the operand width of a
subsequent opcode based on the presence of the WIDE.” (Br. 12). This
statement appears to contradict itself. If the processor adjusts the operand
width of a subsequent opcode due to the “WIDE” opcode, then it would
appear that the wide function is “executed.” Moreover, the Java Virtual
Machine Specification states that the wide instruction modifies the behavior
of another instruction (FF 6), which implies that the wide instruction, when
executed, modifies the behavior of another instruction.
Appellant also contends that using the resolving flag of Grieb to set or
clear the functions of a wide opcode would change the principle of operation
of Grieb (Br. 13). According to Appellant, Grieb’s principle of operation is
“that overloaded opcodes are executed regardless of which overloaded state
is used,” rather than having an opcode with only one executable state. (Id.)
We disagree. We find Appellant’s arguments concerning the
“principle of operation” and the “intended purpose” of Grieb to be factually
incorrect. The so-called principle of operation is not limited to the preferred
embodiment described at column 8, line 21 et seq. of the reference.
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“The use of patents as references is not limited to what the patentees
describe as their own inventions or to the problems with which they are
concerned. They are part of the literature of the art, relevant for all they
contain.” In re Heck, 699 F.2d 1331, 1333 (Fed. Cir. 1983) (quoting In re
Lemelson, 397 F.2d 1006, 1009 (CCPA 1968)). Grieb provides the more
general teaching of dual function opcodes (e.g., col. 1, ll. 10-18; col. 8, ll. 5-
20), and does not teach that dual function opcodes are limited to use of the
exemplary “LDT” operations.
Thus, even assuming that claim 6 requires “a system where one of two
possible states of an opcode is not executed,” and that the wide opcode is
decoded but not executed, both of which are alleged by Appellant, we are
not persuaded that the combination of Grieb and the Java Virtual Machine
Specification fails to teach all that the claim requires. “[I]f a technique has
been used to improve one device, and a person of ordinary skill in the art
would recognize that it would improve similar devices in the same way,
using the technique is obvious unless its actual application is beyond his or
her skill.” KSR, 550 U.S. at 417.

Section 103 rejections of claims 15-17
Appellant has not presented separate arguments for the remaining
claims. Appellant’s arguments for the remaining claims are the same as
those presented for claim 6; i.e., that the wide opcode is not executed, and
the principle of operation of Grieb is changed if the opcode resolving flag is
used with a wide opcode. These arguments are unpersuasive as discussed
above.
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CONCLUSION OF LAW
A person of ordinary skill in the art at the time of invention would
have been able to increase the number of functions associated with the wide
opcode disclosed in the Java Virtual Machine Specification using an opcode
resolving flag as disclosed in Grieb, for the benefit of allowing the number
of opcode functions to exceed the number of available opcodes as taught by
Grieb. We do not find error in the Examiner’s rejection under 35 U.S.C. §
103.

DECISION
The Examiner’s rejection of claims 1-14, 18, and 19 under 35 U.S.C.
§103(a) as being unpatentable over Grieb and the Java Virtual Machine
Specification is affirmed.
The Examiner’s rejection of claims 15 and 16 under 35 U.S.C.
§103(a) as being unpatentable over Grieb, the Java Virtual Machine
Specification, and Gorishek is affirmed.
The Examiner’s rejection of claim 17 under 35 U.S.C. §103(a) as
being unpatentable over Grieb, the Java Virtual Machine Specification,
Gorishek and Petrick is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).

AFFIRMED

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