Ex Parte Chao

Patent Trial and Appeal Board

Oct 9, 2014

12061149 (P.T.A.B. Oct. 9, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/061,149 04/02/2008 Ling-Chiang Chao JCLA24154 7986
23900 7590 10/10/2014
J C PATENTS
4 VENTURE, SUITE 250
IRVINE, CA 92618
EXAMINER
BUI, THA-O H
ART UNIT PAPER NUMBER
2825
MAIL DATE DELIVERY MODE
10/10/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte LING-CHIANG CHAO

Appeal 2012-012214
Application 12/061,149
Technology Center 2800
____________

Before BRADLEY R. GARRIS, BEVERLY A. FRANKLIN, and
N. WHITNEY WILSON, Administrative Patent Judges.

WILSON, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant1 appeals under 35 U.S.C. § 134(a) from the Primary
Examiner’s decision finally rejecting claims 1-16. We have jurisdiction over
the appeal under 35 U.S.C. § 6(b).
We affirm.

1 The real party in interest is Macronix International Co., Ltd. (Appeal Br. 1).
Appeal 2012-012214
Application 12/061,149
2
CLAIMED SUBJECT MATTER
The claimed invention is directed to memory which includes a first-
type memory and a second type memory (Abstract). The first-type memory
is a non-volatile memory having a storage structure with a stack of
electrode/storage/electrode (id., Spec. ¶ 25). Claim 1 is representative of the
claims on appeal, and is reproduced below from the Claims Appendix of the
Appeal Brief (key claim limitations in italics):

1. A memory, comprising:
a first part circuit for a first-type memory; and
a second part circuit for a second-type memory, wherein
the first part circuit and the second part circuit form an
integrated circuit, the first part circuit is formed over the second
part circuit, the first-type memory is a nonvolatile memory
having a storage structure with a stack of
electrode/storage/electrode, and the second-type memory is a
volatile memory, a flash memory, or a memory with a stack of
conductor/storage/conductor.

REJECTIONS
(1) Claims 1-3, 5, 6, 9-11, 13, and 14 are rejected under
35 U.S.C. § 102(b) as being anticipated by Ishii.2
(2) Claims 4, 7-8, 12, 15-16 are rejected under 35 U.S.C. § 103(a) as
being unpatentable over Ishii in view of Walker.3
Appellant states that, for purposes of this appeal, claims 1-8 are
grouped together, as are claims 9-16 (Appeal Br. 2). However, Appellant

2 Ishii, U.S. Patent No. 6,839,260 B2, issued January 4, 2005.
3 Walker et al, U.S. Patent No. 6,888,750 B2, issued May 3, 2005.
Appeal 2012-012214
Application 12/061,149
3
does not make separate arguments for the two groups of claims (see, e.g.,
Appeal Br. 5-6). Nor does Appellant make separate arguments regarding the
obviousness rejection (Appeal Br. 6). Accordingly, we limit our analysis to
the anticipation rejection of claim 1 over Ishii in making our determinations
herein.
DISCUSSION
It is well established that “[a] prior art reference anticipates a patent
claim under 35 U.S.C. § 102(b) if it discloses every claim limitation.” In re
Montgomery, 677 F.3d 1375, 1379 (Fed. Cir. 2012) (citing Verizon Servs.
Corp. v. Cox Fibernet Va., Inc., 602 F.3d 1325, 1336–37 (Fed. Cir. 2010)).
In this instance, Appellant argues that Ishii does not disclose “a
nonvolatile memory having a storage structure with a stack of
electrode/storage/electrode” (Appeal Br. 4-5).
The Examiner finds that this limitation is satisfied by Ishii’s
disclosure of a non-volatile memory array which is arranged in a wiring
layer/storage/wiring layer structure (Ans. 4, citing Ishii Fig. 18, and related
Figs. 1, 3-7, 17-19, and 21). Ishii’s Fig. 18a, which is relied upon by the
Examiner to illustrate this structure, is reproduced below:

Appeal 2012-012214
Application 12/061,149
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Ishii’s FIG. 18a is a conceptual diagram for explaining the
construction of the data processor device according to Ishii’s invention.

The Examiner finds that the wiring layers shown above in FIG. 18a
correspond to the “electrode” elements of the electrode/storage/electrode
structure, and therefore also finds that the structure depicted in FIG. 18a
corresponds to the claimed electrode/storage/electrode structure (see, e.g.
Ans. 4).
In response, Appellant makes two arguments. First, Appellant argues
that the wiring layers disclosed in Fig. 18a of Ishii are not “electrodes” as
recited in the claim. We are not persuaded by this argument. It is well
established that “the PTO must give claims their broadest reasonable
construction consistent with the specification . . .. Therefore, we look to the
specification to see if it provides a definition for claim terms, but otherwise
apply a broad interpretation.” In re ICON Health & Fitness, Inc., 496 F.3d
1374, 1379 (Fed. Cir. 2007). “[A]s applicants may amend claims to narrow
their scope, a broad construction during prosecution creates no unfairness to
the applicant or patentee.” Id.
To the extent possible, claim terms are given their ordinary and
customary meaning, as they would be understood by one of ordinary skill in
the art in question at the time of the invention. Phillips v. AWH Corp., 415
F.3d 1303, 1312-13 (Fed. Cir. 2005) (en banc). Idiosyncratic language,
highly technical terms, or terms coined by the inventor are best understood
by reference to the Specification. Id. at 1315-16. Extrinsic evidence such as
dictionary definitions may be utilized when construing claim terms, so long
as the extrinsic evidence does not contradict any definition found in the
Specification, including the claims and written description. Cf. Advanced
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Application 12/061,149
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Fiber Tech. (AFT) Trust v. J & L Fiber Servs., Inc., 674 F.3d 1365, 1374-75
(Fed. Cir. 2012) (internal citations omitted).
In this instance, the Specification does not define the term “electrode.”
The Examiner construes the term “electrode” as “connecting or wiring that
depend from the top view and/or the side view,” but does not provide any
explanation for that construction (Ans. 10). Appellant provides a dictionary
definition of “electrode”: “an element in a semiconductor device (as a
transistor) that emits or collects electrons or holes or controls their
movements" (Appeal Br. 6, citing the on-line Merriam-Webster Dictionary).
Appellant argues that Ishii’s system does not meet this definition
at least because the upper or lower wiring layer in Ishii is
simply for electrically connecting the non-volatile memory
array to another level of devices, it is apparently not an
element of a semiconductor device or a transistor among the
millions of devices or transistors in the non-volatile memory
array

(id., italic emphasis in original, bolded emphasis added).

As illustrated by the quoted section above, Appellant only argues that
Ishii’s wiring is “apparently” not an element of a semi-conductor device or
transistor, and therefore does not meet the claimed limitation of an
“electrode.” However, Appellant has not provided persuasive evidence to
support the contention that Ishii’s wiring layer does not meet Appellant’s
proffered definition of electrode. Therefore, on balance, we determine that
Appellant has not convinced us that the Examiner’s determination that
Ishii’s disclosed structure meets the claimed electrode/storage/electrode
structure is erroneous.
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Application 12/061,149
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Appellant’s second argument urging reversal of the anticipation
rejection of claim 1 is that the Examiner’s interpretation of Ishii’s disclosure
(that Ishii’s wiring/storage/wiring structure corresponds to the claimed
electrode/storage/electrode structure) is illogical (and presumably erroneous)
because that interpretation would be mean that “the non-volatile memory
array of Ishii would be a part (one layer in the 3-layer stack) of itself”
(Appeal Br. 5-6, Reply Br. 2). Appellant’s argument is not persuasive
because, as found by the Examiner, Ishii’s Fig. 18a shows quite plainly the
wiring layer/storage/wiring layer structure relied on by the Examiner to
anticipate the claimed electrode/storage/electrode structure. To the extent
that Appellant is attempting to argue that Ishii’s disclosed non-volatile
memory array includes the claimed electrodes, such an argument has not
been supported by credible evidence.
Accordingly, we determine that Appellant has not shown reversible
error in the anticipation rejection of claim 1 over Ishii. Since, as noted
above, Appellant does not make separate arguments against the obviousness
rejections, we affirm that rejection also.
CONCLUSION
We AFFIRM the rejection of claims 1-3, 5, 6, 9-11, 13, and 14 under
35 U.S.C. § 102(b) as being anticipated by Ishii.
We AFFIRM the rejection of claims 4, 7-8, 12, 15-16 under
35 U.S.C. §103(a) as being unpatentable over Ishii in view of Walker.

Appeal 2012-012214
Application 12/061,149
7
No time period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a). See
37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED
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