Ex Parte Chandra et al

Patent Trial and Appeal Board

Apr 24, 2017

13899731 (P.T.A.B. Apr. 24, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/899,731 05/22/2013 Prashant R. Chandra 104985-0243 7217
23524 7590 04/26/2017
FOT FY Rr T ARDNFR T T P
EXAMINER
3000 K STREET N.W. BLANTON, JOHN D
SUITE 600
WASHINGTON, DC 20007-5109 ART UNIT PAPER NUMBER
2466
NOTIFICATION DATE DELIVERY MODE
04/26/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ipdocketing @ foley. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte PRASHANT R. CHANDRA, THOMAS A. VOLPE,
and MARK BRADLEY DAVIS
Appeal 2016-008612
Application 13/899,7311
Technology Center 2400
Before JOSEPH L. DIXON, NORMAN H. BEAMER,
and JAMES W. DEJMEK, Administrative Patent Judges.
BEAMER, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1—25. We have jurisdiction over the pending
rejected claims under 35 U.S.C. § 6(b).
We affirm.
1 Appellants identify III Holdings 2, LLC as the real party in interest.
(App. Br. 2.)
Appeal 2016-008612
Application 13/899,731
THE INVENTION
Appellants’ disclosed and claimed invention is directed to time
synchronization between nodes of a switched interconnect fabric. (Spec.,
Title.)
Claim 1, reproduced below, is illustrative of the subject matter on
appeal:
1. A data processing node, comprising:
a local clock configured to maintain a local time of the
data processing node;
a slave port connected through a node interconnect
structure to a parent node, wherein the parent node is
configured to operate in a time synchronized manner with a
fabric time of the node interconnect structure; and
a time synchronization module coupled to the local clock
and the slave port, wherein the time synchronization module is
configured to:
collect parent-centric time synchronization
information by exchanging a plurality of messages with
the parent node via the slave port;
compute the fabric time based on the local time
provided by the local clock and the parent-centric time
synchronization information; and
provide the fabric time for use by one or more
time-based functionality of the data processing node;
wherein the time synchronization module includes a
dedicated hardware computation processor on the data
processing node.
REJECTIONS
The Examiner rejected claims 1, 3, 4, 6, 8, 9, 11, 13—15, 17, 18, and
21—23 under 35 U.S.C. § 103(a) as being unpatentable over Chandra et al.
(US 2014/0122755 Al, pub. May 1, 2014) and Master et al. (US
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Application 13/899,731
2003/0105949 Al, pub. June 5, 2003) (hereafter, “Master”).2 (Final Act. 3—
7.)
The Examiner rejected claims 2, 5, 7, 10, 12, 16, 19, 20, 24, and 25
under 35 U.S.C. § 103(a) as being unpatentable over Chandra, Master, and
Zuccolotto et al. (US 2006/0195780 Al, pub. Aug. 31, 2006). (Final Act. 8—
10.)
ISSUE ON APPEAL
Appellants’ arguments in the Appeal Brief present the following
issue:3
Whether the Examiner erred in finding the combination of Chandra
and Master teaches or suggests the independent claim 1 limitation, “wherein
the time synchronization module includes a dedicated hardware computation
processor on the data processing node,” and the commensurate limitation
recited in independent claims 11 and 17. (App. Br. 10-12.)
2 The Examiner and Appellants refer in the papers to a different patent
assigned to the same assignee and also including Paul L. Master as a named
inventor: Master et al. (US 2004/0268096 Al, pub. Dec. 30, 2004)
(hereafter “Master II”). The two “Master” published applications include
substantially the same disclosures to the extent relied on and discussed by
Appellants and the Examiner. We treat all references to Master II as
intended to refer to the corresponding disclosures in Master.
3 Rather than reiterate the arguments of Appellants and the findings of the
Examiner, we refer to the Appeal Brief (filed Jan. 22, 2016); the Reply Brief
(filed Sept. 16, 2016); the Final Office Action (mailed Aug. 12, 2015); and
the Examiner’s Answer (mailed July 27, 2016) for the respective details.
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Appeal 2016-008612
Application 13/899,731
ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
arguments the Examiner erred. We disagree with Appellants’ arguments,
and we adopt as our own (1) the pertinent findings and reasons set forth by
the Examiner in the Final Office Action from which this appeal is taken
(Final Act. 3—10) and (2) the corresponding findings and reasons set forth by
the Examiner in the Examiner’s Answer in response to Appellants’ Appeal
Brief (Ans. 10-15). We concur with the applicable conclusions reached by
the Examiner, and emphasize the following.
In finding Chandra and Master teach or suggest the claim limitation at
issue, the Examiner relies on the disclosure in Master of an adaptive
computing engine (ACE) integrated circuit including computational
elements with dedicated hardware computation processors:
within computation units 200, different computational elements
(250) are implemented directly as correspondingly different
fixed (or dedicated) application specific hardware, such as
dedicated multipliers, complex multipliers, and adders.
(Final Act. 4—5; Master Figs. 4, 5,1 56; see Master II, Figs. 1,3,148.)
Appellants argue the matrix controller in Master is “not a ‘dedicated’
processor on a ‘data processing node,’ but rather it is a master device
coupled to multiple matrices 150A through 150N via a network. ” (App.
Br. 10). However, as the Examiner finds, the computational units 250
satisfy the limitation at issue, not the matrix controller 150:
[T]he computational units configured to perform application
specific functions preprogrammed by the “matrix controller”
are cited by the Examiner as teaching the “dedicated hardware
computation processor”. The “matrix controller” does not
control the computational units rather the “matrix controller”
configures over the network . . . the computational units to
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Application 13/899,731
perform application specific functions. The “matrix controller”
programs the computational elements . . . within a respective
computational unit. . . based on designed functionality. After
the computational unit is “wired”, the computational unit
executes the application specific function independently from
the “matrix controller”.
(Ans. 11.)
Appellants further argue Master is non-analogous art, because it
involves digital imaging apparatus rather than computer platform
architecture. (App. Br. 11.) This argument is not persuasive:4
Two separate tests define the scope of analogous prior art: (1)
whether the art is from the same field of endeavor, regardless of
the problem addressed and, (2) if the reference is not within the
field of the inventor’s endeavor, whether the reference still is
reasonably pertinent to the particular problem with which the
inventor is involved.
In re Klein, 647 F.3d 1343, 1348 (Fed. Cir. 2011) (quoting In re Bigio, 381
F.3d 1320, 1325 (Fed. Cir. 2004) (emphases added). We agree with the
Examiner that Master is reasonably pertinent to the problems addressed by
the Application — disclosing the application of computational units on other
data processing applications besides digital imaging. (Ans. 14.)
4 Appellants make a similar conclusory argument regarding the obviousness
rejection of claims 2, 5, 7, 10, 12, 16, 19, 20, 24, and 25 over Chandra,
Master, and Zuccolotto: “Applicant respectfully disagrees that Chandra and
Zuccolotto are ‘from similar fields of endeavor.’” (App. Br. 13.) Based on
the Examiner’s findings to the contrary, and based in the same
considerations as discussed with respect to the Master reference, we are not
persuaded the Examiner errs. (See Final Act. 8.)
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Appellants also argue the Examiner errs in finding a reason to
combine Chandra and Master. (App. Br. 12.) This conclusory argument is
unpersuasive — as the Examiner finds, “A person of ordinary skill in the art
would know that processor executing hardware components disclosed by
Master versus a software program running on general purpose processor
disclosed by Chandra would run faster and more efficiently.” (Ans. 15.)
Appellants do not point to any evidence of record that the resulting
combination would be “uniquely challenging or difficult for one of ordinary
skill in the art” or “represented an unobvious step over the prior art.”
Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir.
2007) (citing KSR Int 7 Co. v. Teleflex Inc., 550 U.S. 398, 418-19 (2007)).
The Examiner’s findings are reasonable because the skilled artisan would
“be able to fit the teachings of multiple patents together like pieces of a
puzzle” because the skilled artisan is “a person of ordinary creativity, not an
automaton.” KSR, 550 U.S. at 420-21. We are persuaded the claimed
subject matter exemplifies the principle that “[t]he combination of familiar
elements according to known methods is likely to be obvious when it does
no more than yield predictable results.” Id. at 416.
CONCLUSION
For the reasons stated above, we sustain the obviousness rejections of
claims 1,11, and 17 over Chandra and Master. We also sustain the
obviousness rejections of claims 3, 4, 6, 8, 9, 13—15, 18, and 21—23 over
Chandra and Master, which rejections are not argued separately with
particularity.
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As also discussed above, we sustain the obviousness rejection of
claims 2, 5, 7, 10, 12, 16, 19, 20, 24, and 25 over Chandra, Master, and
Zuccolotto.
DECISION
We affirm the Examiner’s rejections of claims 1—25.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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