Ex Parte Champion et al

Patent Trial and Appeal Board

Feb 27, 2013

10959535 (P.T.A.B. Feb. 27, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/959,535 10/05/2004 Mark Champion 7114-81399-US 3272
37123 7590 02/28/2013
FITCH EVEN TABIN & FLANNERY, LLP
120 SOUTH LASALLE STREET
SUITE 1600
CHICAGO, IL 60603-3406
EXAMINER
CHOW, JEFFREY J
ART UNIT PAPER NUMBER
2679
MAIL DATE DELIVERY MODE
02/28/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte MARK CHAMPION and BRIAN DOCKTER
____________

Appeal 2011-003600
Application 10/959,535
Technology Center 2600
____________

Before JOSEPH L. DIXON, ST. JOHN COURTENAY III, and
CARLA M. KRIVAK, Administrative Patent Judges.

COURTENAY, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2011-003600
Application 10/959,535
2
STATEMENT OF THE CASE
The Patent Examiner finally rejected claims 1-54, 81-88, 93-110, 112,
and 114. Claims 55-80, 89-92, 111, and 113 were canceled. (App. Br. 4).1
Appellants appeal therefrom under 35 U.S.C. § 134(a). We have jurisdiction
under 35 U.S.C. § 6(b).
We reverse.
INVENTION
This invention relates to video display systems and frame buffers.
(Spec. 1). Claim 1, reproduced below, is illustrative of the claimed subject
matter:
Claim 1: A checkerboard buffer, comprising
[a] a data source, providing data in pairs in a first order;
[b] a data destination, receiving data in a second order;
[c] at least two memory devices, each memory device having a
plurality of memory locations, where data is stored in parallel to
the memory devices and retrieved in parallel from the memory
devices;
[d] a first data switch coupled to the data source and each of the
memory devices, [d1] where the first data switch controls
which data of the pairs is stored to which memory device, [d2]
wherein the first data switch is configured to swap which data
of the pairs is stored in which of the memory devices; and
[e] a second data switch coupled to the data destination and
each of the memory devices, where the second data switch

1 Claim 112 is erroneously listed as canceled on page 4 of the Appeal Brief
(“Claims 55-80, 89-92, 111-113 were canceled during prosecution.”).
However, claim 112 is also listed as being appealed (App. Br. 4; App.
Br. Appendix 40; Ans. 2) and was not canceled. (See Response to Office
Action, page 15, dated October 19, 2009). Therefore, claims 1-54, 81-88,
93-110, 112, and 114 are before us on appeal.
Appeal 2011-003600
Application 10/959,535
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controls providing data to the data destination according to the
second order.
(Disputed limitation emphasized).
REJECTIONS
R1: Claims 1-12, 14-32, 36, 40-43, 45-54, 81-88, 104, 112, and 114 stand
rejected under 35 U.S.C. § 103 (a) in view of Applicant’s Admitted Prior Art
(herein after referred to as "AAPA"), in view of Jiang (U.S. Patent No.
6,614,441 B1), and in further view of Owada (U.S. Patent No. 6,819, 334
B1).

R2: Claim 13 stands rejected under 35 U.S.C. § 103(a) in view of AAPA,
Jiang, and Owada, and in further view of Kao (U.S. Patent No. 5,561,777).

R3: Claims 33 and 35 stand rejected under 35 U.S.C. § 103 (a) in view of
AAPA, Jiang, and Owada, and in further view of Farley (U.S. Patent No.
5,117,289).

R4: Claim 34 stands rejected under 35 U.S.C. § 103(a) in view of AAPA,
Jiang, Owada, and Farley and further in view of Hastings (U.S. Patent No.
6,349,143 B1).

R5: Claims 37-39 and 108-110 stand rejected under 35 U.S.C. § 103(a) in
view of AAPA, Jiang, and Owada and in further view of Arbeiter (U.S.
Patent No. 4,603,350).

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Application 10/959,535
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R6: Claim 44 stands rejected under 35 U.S.C. 103 (a) in view of AAPA,
Jiang, and Owada and in further view of Wertz (U.S. Patent No. 4,680,599).

R7: Claims 93-103 and 106 stand rejected under 35 U.S.C. § 103(a) in view
of AAPA, Jiang, and Owada and in further view of Haikawa (U.S. Patent
No. 5,136,394).

R8: Claim 105 stands rejected under 35 U.S.C. § 103(a) in view of AAPA,
Jiang, Owada, and Haikawa and in further view of McAulay (U.S. Patent
No. 4,811,210).

R9: Claim 107 stands rejected under 35 U.S.C. § 103(a) in view of AAPA,
Jiang, and Haikawa, and in further view of Hasegawa (U.S. Patent No.
4,890,165).

ANALYSIS
Issue: Under § 103, did the Examiner err in finding that the cited
references, either alone or in combination, would have taught or suggested
[d1] "where the first data switch controls which data of the pairs is stored to
which memory device," within the meaning of claim 1, and the
commensurate language of claims 81 and 93?
Appellants contend:
To store pixel data, memories 410 and 415 are put in write
mode and address multiplexor 445 is set to connect first input
440 to output 460. Video source 405 provides pixel data for a
first pixel to first data bus 425 ... and pixel data for a second
pixel to second data bus 430 ... First data bus 425 provides its
pixel data to first memory 410 and second data bus 430
Appeal 2011-003600
Application 10/959,535
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provides its pixel data to second memory 415 (see AAPA,
[0018] and [0019]).
As such, it is clear that the multiplexor 445 is disclosed
as switching between reading in data, i.e. being connected to
video source and writing data, i.e. being connected to video
destination.
(App. Br. 16-17).
The Examiner disagrees:
The Examiner cited Fig. 4 and [0018] which expressly teaches
of a multiplexor 445 (well known in the art as a switching
means - therefore the first switch) which is coupled to each of
the two memory devices (410 and 415). The multiplexor
(switch) is further coupled to the data source (405). This
portion of citations by AAPA expressly teaches "a first data
switch coupled to the data source and each of the memory
devices". This portion also teaches "wherein the first data
switch is configured to swap which data of the pairs is stored in
which of the memory devices" because it expressly states
within the AAPA that multiplexor 445 receives the control
signal which causes the first output or second output to either
the first or the second memory and also control of whether the
multiplexor reads or writes.
(Ans. 61).
Appellants' contentions are persuasive. The Examiner erroneously
finds that AAPA's multiplexor ("first data switch") "controls which data of
the pairs is stored to which memory device." (Ans. 61). We find
multiplexor 445 outputs memory addresses, not pixel data, to memories 410
and 415. (Spec. 6). We also find AAPA teaches that video source 405 (not
multiplexor 445) provides first pixel data to the first memory 410 via the
first data bus 425. (Spec. 6). AAPA further teaches that video source 405
(not the multiplexor 445) provides second pixel data to the second memory
415 via the second data bus 430. (Id.).
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Therefore, we are persuaded the Examiner erred by finding that
AAPA's multiplexor 445 "controls which data of the pairs is stored to which
memory device" (claim 1) because AAPA's video source 405 "controls
which data of the pairs is stored to which memory device." (Spec. 6; App.
Br. 16-17). Accordingly, we reverse the rejection of independent claim 1
and independent claims 81 and 93, which recite the same limitation in
commensurate form.
Regarding the rejections of the remaining dependent claims, the
Examiner does not allege that the additionally cited references cure the
deficiency discussed above with respect to the independent claims. (Ans.
60-70). Therefore, we reverse the rejections of the remaining dependent
claims.

DECISION
We reverse the Examiner's rejections of claims 1-54, 81-88, 93-110,
112, and 114 under § 103.
ORDER
REVERSED

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