13230131 (P.T.A.B. Mar. 26, 2018)

Ex Parte Chachad et al

Patent Trial and Appeal BoardMar 26, 2018

13230131 (P.T.A.B. Mar. 26, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 13/230, 131 09/12/2011 23494 7590 03/28/2018 TEXAS INSTRUMENTS IN CORPORA TED P 0 BOX 655474, MIS 3999 DALLAS, TX 75265 FIRST NAMED INVENTOR Abhijeet Ashok Chachad UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. TI-69963 2326 EXAMINER SUN, CHARLIE ART UNIT PAPER NUMBER 2196 NOTIFICATION DATE DELIVERY MODE 03/28/2018 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): uspto@ti.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte ABHIJEET ASHOK CHACHAD, RAGURAM DAMODARAN, RAMAKRISHNAN VENKA TASUBRAMANIAN, and JOSEPH RAYMOND MICHAEL ZBICIAK Appeal2017-007454 Application 13/230, 131 1 Technology Center 2100 Before JOHN A. JEFFERY, JAMES R. HUGHES, and JOHN D. HAMANN, Administrative Patent Judges. HAMANN, Administrative Patent Judge. DECISION ON APPEAL Appellants file this appeal under 35 U.S.C. Â§ 134(a) from the Examiner's Final Rejection of claims 1 and 16. We have jurisdiction under 35 U.S.C. Â§ 6(b). We affirm. 1 According to Appellants, the real party in interest is Texas Instruments Incorporated. App. Br. 3. Appeal2017-007454 Application 13/230, 131 THE CLAIMED INVENTION Appellants' claimed invention "relates to management of memory access by multiple requesters, and in particular to access to a shared memory resource in a system on a chip with multiple cores." Spec. i-f 2. Claim 1 is illustrative of subject matter of the appeal and is reproduced below. 1. A method of operating a queuing requester for access to a memory system, the method comprising: receiving transaction requests from two or more requestors for access to the memory system, wherein each transaction request includes an associated priority value; forming one request queue of the received transaction requests, wherein each received transaction request is stored in a transaction request stage within the request queue, each transaction request stage including data corresponding to the transaction request and data corresponding to the associated priority value; determining a highest associated priority value of all pending transaction requests within the request queue; associating said determined highest associated priority value with an oldest transaction request within the request queue; and providing the oldest transaction request in the request queue to the memory system for each clock cycle. REJECTIONS2 ON APPEAL (1) The Examiner rejected claim 1 under 3 5 U.S. C. Â§ 10 3 (a) as being unpatentable over the combination of Vaz et al. (US 2011/0246688 Al; published Oct. 6, 2011) (hereinafter "Vaz"); Howard (US 2004/0172631 Al; published Sept. 2, 2004); Youngcheng Li et al., Disk Scheduling with Dynamic Request Priorities, Dept. of Computer Sci., Univ. of Ill. at Urbana- 2 The Examiner withdrew theÂ§ 112 rejection of claim 16. Ans. 4. 2 Appeal2017-007454 Application 13/230, 131 Champaign, 1-20 (Mar. 1996) (hereinafter "Li"); and Ryken (US 2003/0236963 Al; published Dec. 25, 2003). (2) The Examiner rejected claim 16 under 35 U.S.C. Â§ 103(a) as being unpatentable over the combination of Vaz, Howard, Li, Ryken, and Uchiyama et al. (US 2010/0131718 Al; published May 27, 2010) (hereinafter "Uchiyama"). ANALYSIS We have reviewed the Examiner's rejections in light of Appellants' contentions that the Examiner erred. In reaching our decision, we consider all evidence presented and all arguments made by Appellants. We disagree with Appellants' arguments and we incorporate herein and adopt as our own the findings, conclusions, and reasons set forth by the Examiner in (1) the June 27, 2016 Final Office Action ("Final Act." 2-14); (2) the September 8, 2016 Advisory Action ("Adv. Act." 2); and (3) the February 8, 2017 Examiner's Answer ("Ans." 2-15). We highlight and address, however, specific findings and arguments below for emphasis. (1) Whether fundamentally incompatible Appellants argue that Li's teaching of "plural queues, one for each priority level," is fundamentally incompatible with Vaz's teaching of a single queue, and that these teachings cannot be combined. App. Br. 6 (citing Vaz i-f 15; Li Fig. 3), 10. Appellants further argue that "determining a highest priority request from a single queue differs from and is unobvious over selection of the highest priority request from plural queues, one for each priority level." Id. 3 Appeal2017-007454 Application 13/230, 131 The Examiner finds that the relevant teachings of Vaz and Li are properly combined. Ans. 4--5; Final Act. 5-7; Adv. Act. 2. The Examiner finds that Vaz teaches a single queue design and Vaz "is modified to include the features of boosting the oldest transaction request to the highest priority," as taught by Li, to arrive at the claimed invention. Ans. 4 (citing Vaz i-f 5; Li Fig. 3 ). The Examiner notes that "(only this feature is taken from Li [not the two queue design of Li])." Id. The Examiner also finds that although Li teaches multiple queue systems "having prioritized requests[,] and Vaz teaches a single queue system having prioritized requests, one of ordinary skill in the art understands that the concept of boosting the oldest request to the highest priority would be applicable and could be implemented in any queue design with prioritized requests." Ans. 5 (emphasis omitted). We agree with the Examiner's findings and adopt them as our own. It is well settled that "it is not necessary that the inventions of the references be physically combinable to render obvious the invention under review." In re Sneed, 710 F.2d 1544, 1550 (Fed. Cir. 1983). "Combining the teachings of references does not involve an ability to combine their specific structures." In re Nievelt, 482 F.2d 965, 968 (CCPA 1973). The relevant inquiry is whether the claimed subject matter would have been obvious to those of ordinary skill in the art in light of the combined teachings of those references. See In re Keller, 642 F.2d 413, 425 (CCPA 1981); see also KSR Int'! Co. v. Teleflex Inc., 550 U.S. 398, 420-21 (2007) (finding the skilled artisan would "be able to fit the teachings of multiple patents together like pieces of a puzzle" because the skilled artisan is "a person of ordinary creativity, not an automaton"). 4 Appeal2017-007454 Application 13/230, 131 Furthermore, Appellants' assertions that Vaz and Li are "fundamentally incompatible" and it would have been "unobvious" to combine their teachings are conclusory and Appellants provide no persuasive evidence supporting their assertions. See App. Br. 6; see also In re Pearson, 494 F.2d 1399, 1405 (CCPA 1974) ("Attorney's argument in a brief cannot take the place of evidence."). (2) Associating highest priority with oldest request Appellants argue the combination of Vaz, Howard, Li, and Ryken fails to teach or suggest "associating said determined highest associated priority value with an oldest transaction request within the request queue," as recited in claims 1 and 16. App. Br. 7, 10-11. According to Appellants, claim 1 provides that "the priority value of the oldest transaction request in the queue is elevated whenever a higher priority transaction is in the queue." Id. Appellants argue that Li's teachings "prevent such an elevation when the length of the high priority queue exceeds the threshold. Thus there are circumstances (length of high priority queue exceeds threshold) where claim 1 would elevate the priority of the oldest request in the queue and Li ... would not." Id. (citing Li Fig. 3). Appellants argue thus "[t]he existence of conditions handled differently in the claim than in the reference is evidence ofunobviousness." Id. The Examiner finds, and we agree, that the combination teaches or suggests the disputed limitation. E.g., Ans. 7-8. As discussed above (see supra Â§ 1 ), the Examiner properly combines Vaz' s teaching of a single queue design with Li's teaching of "boosting the oldest transaction request to the highest priority." See Ans. 4 (citing Vaz i-f 5; Li Fig. 3); see also Ans. 7-8 (reiterating that Li teaches elevating the oldest transaction request within the 5 Appeal2017-007454 Application 13/230, 131 request queue to a determined highest priority value and finding that claim 1 does not require Appellants' "particular triggering condition"). Furthermore, we are unpersuaded by Appellants' argument that one of ordinary skill in the art would limit Li's teachings as argued by Appellants (i.e., elevating the priority of an oldest request only when the length of the high priority queue does not exceed a threshold). Rather, "[a] reference may be read for all that it teaches, including uses beyond its primary purpose." See In re Mouttet, 686 F.3d 1322, 1331 (Fed. Cir. 2012); EWP Corp. v. Reliance Universal Inc., 755 F.2d 898, 907 (Fed. Cir. 1985) ("A reference must be considered for everything it teaches by way of technology and is not limited to the particular invention it is describing and attempting to protect."). (3) Oldest transaction request within the request queue Appellants argue the combination of Vaz, Howard, Li, and Ryken fails to teach or suggest that the claimed "associating" is with respect to "an oldest transaction request within the request queue," as recited in claims 1 and 16. App. Br. 7-8, 11-12. More specifically, Appellants argue that "[i]n the context of the two queues disclosed in Li et al, this must be the oldest request in the two queues including the high priority queue and the low priority queue. Li et al selects the older request from only the low priority queue." App. Br. 8 (providing example of a purported two queue design where high priority requests are received while the threshold is exceeded and few low priority requests exist so that when the pending high priority requests drop below the threshold, the oldest low priority request is elevated to high priority despite there being older requests already in the high priority queue). 6 Appeal2017-007454 Application 13/230, 131 The Examiner finds, and we agree, that the combination teaches or suggests the disputed limitation. Ans. 7-8. As discussed above (see supra Â§ 1 ), the Examiner properly combines Vaz' s teaching of a single queue design with Li's teaching of "boosting the oldest transaction request to the highest priority." See Ans. 4 (citing Vaz i-f 5; Li Fig. 3); see also Ans. 7-8. Appellants incorrectly narrow the applicability of Li's teachings to two queue designs. See Mouttet, 686 F.3d at 1331; EWP Corp., 755 F.2d at 907 ("A reference must be considered for everything it teaches by way of technology and is not limited to the particular invention it is describing and attempting to protect."). Instead, the Examiner combines Li's teachings of boosting the oldest transaction request to the highest priority with Vaz's single queue design. Ans. 4 (citing Vaz i-f 5; Li Fig. 3); see also In re Keller, 642 F.2d at 425 (finding the correct focus is whether the disputed limitation would have been obvious to one of ordinary skill in the art in light of the combined teachings of the references). (4) Providing the oldest transaction request Appellants argue the combination of Vaz, Howard, Li, and Ryken fails to teach or suggest "providing the oldest transaction request in the request queue to the memory system for each clock cycle," as recited in claim 1, and similarly recited in claim 16. App. Br. 8-9, 12-13. Appellants argue that this limitation requires "[ u ]nconditionally providing this oldest transaction to the memory system [and] requires these transactions to be handled in a first-in-first-out manner." App. Br. 8. Appellants argue that Li instead teaches "scheduling a high priority request from the high priority queue if this queue is not empty." Id. at 9 (citing Li Fig. 3). Appellants argue that "this scheduled high priority request is older than all low priority 7 Appeal2017-007454 Application 13/230, 131 requests." Id. Appellants also argue that when Li "upgrades the priority of the oldest low prior request," it "does not automatically schedule the priority elevated oldest low prior request." Id. The Examiner finds that the combination teaches the disputed limitation. Ans. 8-10; Final Act. 7. As discussed above, the Examiner finds "Vaz teaches a single queue, and Li discloses a feature where the priority of the oldest request in a queue is promoted." Ans. 10; see also supraÂ§ 1. The Examiner concludes that it would have been obvious to one of ordinary skill in the art to add Li's step of providing the oldest transaction request at the highest priority to Vaz' s single queue design "because it is a common technique in the art to increase the priority of a request if it has not been served for a long time." Final Act. 7 (citing Li 2). We agree with the Examiner's findings and adopt them as our own. Li teaches elevating the oldest lower priority request to the highest priority (i.e., the high priority que ), and thus, for a one queue design, one of ordinary skill in the art would have found it obvious to elevate the oldest request to the highest priority for the queue so as to be served next. See Li Fig. 3, 2; see also KSR, 550 U.S. at 418 ("[T]he [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim, for a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ."); In re Preda, 401 F .2d 825, 826 (CCPA 1968) ("[I]t is proper to take into account not only specific teachings of the references but also the inferences which one skilled in the art would reasonably be expected to draw therefrom."). 8 Appeal2017-007454 Application 13/230, 131 (5) Arbitrating among the oldest transaction requests Appellants argue the combination of Vaz, Howard, Li, Ryken, and Uchiyama fails to teach or suggest "providing the oldest transaction request in the request queue for shared memory system arbitration for each clock cycle; arbitrating among the oldest transaction request for each processor; and granting access to a shared memory system to the transaction request from among the oldest transaction requests provided by the plural processors having the highest priority," as recited in claim 16. App. Br. 13-14. Appellants argue that these limitations require "two levels of transaction request handling" where "[t]he first level is each of the plural processors" and "[t]he second level is among processors for access to the shared memory system." App. Br. 13. Appellants contend that the combination does "not make obvious these two levels of priority handling." App. Br. 13-14 (citing Spec. i-f 19) (explaining why two levels of priority handling are useful). The Examiner finds that the combination teaches the disputed limitations. Ans. 14--15; Final Act. 10-14. More specifically, the Examiner finds "Vaz/Howard/Li/Ryken elevates the priority at the first level, and Uc[hiyama] (in [0010]) discloses a way of creating a 2nd level of a system and granting access to shared memory system to the oldest transaction request having the highest priority determined at the 1st level (by Vaz/Howard/Li/Ryken). As a whole, the combination teaches the claimed invention in claim 16 completely." Ans. 14--15. We are unpersuaded by Appellants' arguments, which are conclusory. See 37 C.F.R. Â§ 41.37(c)(l)(iv); In re Lovin, 652 F.3d 1349, 1357 (Fed. Cir. 2011) (holding that "the Board reasonably interpreted Rule 41.37 to require more substantive arguments in an 9 Appeal2017-007454 Application 13/230, 131 appeal brief than a mere recitation of the claim elements and a naked assertion that the corresponding elements were not found in the prior art"). As discussed above in Â§ 1, the combination of Vaz, Howard, Li, and Ryken teaches or suggests priority handling regarding the oldest requests. We agree with the Examiner that when Uchiyama's teachings are added to the prior combinations' teachings, the entire combination teaches or suggests the disputed limitations, including arbitrating among the oldest requests for each processor and granting appropriate access. See supra Â§ 1; Uchiyama i-f 10. CONCLUSION Based on our findings above, we sustain the Examiner'sÂ§ 103 rejection of claim 1 and Â§ 103 rejection of 16. DECISION We affirm the Examiner's decision rejecting claims 1 and 16. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. Â§ 1.136(a)(l )(iv). AFFIRMED 10