Ex Parte Bybell et al

Patent Trial and Appeal Board

Feb 17, 2017

13785188 (P.T.A.B. Feb. 17, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
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APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/785,188 03/05/2013 Anthony J. Bybell POU920120041US2 7645
46429 7590 02/22/2017
C ANTOR mT RT TRN T T P-TRM POT TOHKFFPSTF EXAMINER
20 Church Street WESTBROOK, MICHAEL L
22nd Floor
Hartford, CT 06103 ART UNIT PAPER NUMBER
2139
NOTIFICATION DATE DELIVERY MODE
02/22/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ANTHONY J. BYBELL and MICHAEL K. GSCHWIND
Appeal 2016-005867
Application 13/785,1881
Technology Center 2100
Before ST. JOHN COURTENAY III, MATTHEW J. McNEILL, and
ALEX S. YAP, Administrative Patent Judges.
McNEILL, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1 and 3-9, which are all the claims pending in this
application.2 We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
1 According to Appellants, the real party in interest is International Business
Machines Corporation. Br. 1.
2 Claim 2 is canceled. Br. 1.
Appeal 2016-005867
Application 13/785,188
STATEMENT OF THE CASE
Introduction
Appellants’ application relates to sending a request to access a desired
block of memory. Abstract. Claim 1 is illustrative of the appealed subject
matter and reads as follows:
1. A computer implemented method for accessing memory
locations, the method comprising:
receiving a request to access a desired block of memory
located in one of a plurality of non-contiguous virtual memory
regions, the request comprising an effective address consisting
of an effective segment identifier (ESID) and a linear address,
the linear address consisting of a most significant portion and a
byte index;
locating, by a processor, an entry corresponding to the
effective address in a segment lookaside buffer (SLB) that
includes multiple entries that include radix page table pointers
(RPTPs) corresponding to the plurality of non-contiguous
virtual memory regions; and
based on the located entry corresponding to the effective
address in the SLB including an RPTP corresponding to the one
of the plurality of non-contiguous virtual memory regions,
performing:
using the RPTP from the located entry to locate a
translation table of a hierarchy of translation tables;
using the located translation table to translate the
entirety of the most significant portion of the linear
address to obtain an address of a block of memory; and
based on the obtained address, performing the
requested access to the desired block of memory.
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Appeal 2016-005867
Application 13/785,188
The Examiner’s Rejections
Claims 1,3,7, and 9 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Davis (US 2007/0079106 Al; Apr. 5, 2007) and Heil (US
2010/0058026 Al; Mar. 4, 2010). Final Act. 2-7.
Claim 8 stands rejected under 35 U.S.C. § 103(a) as unpatentable over
Davis, Heil, and Hall (US 2010/0125708 Al; May 20, 2010). Id. at 7-9.
Claims 4-6 stand rejected under 35 U.S.C. § 103(a) as unpatentable
over Davis, Heil, and Grisenthwaite (US 2011/0225389 Al; Sept. 15, 2011).
Id. at 10-13.
Claims 1 and 3-9 stand provisionally rejected on the ground of
nonstatutory double patenting as being unpatentable over claims 1, 3-7, 15,
and 17-24 of Application No. 13/517,758 in view of Davis. Id. at 14-15.
ANALYSIS
We have reviewed the Examiner’s rejections in consideration of
Appellants’ contentions and the evidence of record. Appellants persuade us
the Examiner fails to establish the claims are unpatentable over the cited
prior art.
The Examiner finds the combination of Davis and Heil teaches or
suggests “using the located translation table to translate the entirety of the
most significant portion of the linear address to obtain an address of a block
of memory,” as recited in claim 1. Final Act. 4-5; Ans. 2-3. Specifically,
the Examiner finds Davis teaches a linear address (items 306-308), which
includes a most significant portion consisting of high page 306 and low page
307. Id. at 3. The Examiner finds both high page 306 and low page 307 are
“used in the translation as a whole” to obtain an address of a block of
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Appeal 2016-005867
Application 13/785,188
memory. Ans. 3 (citing Davis, Fig. 3). Davis teaches high page 306 is used
to calculate an indexing address of a page line in a page table. Id. (citing
Davis H47, 51, 56). The page line is used in conjunction with low page
307 and selector 328 to obtain the real page number 309, which is an address
of a block of memory. Id. (citing Davis H 47, 51, 56). The Examiner finds
the entirety of the most significant portion (both high page 306 and low page
307) is, therefore, used in the translation to obtain an address of a block in
memory. Id. at 3—4.
Appellants argue the Examiner erred because Davis teaches
translating low page 307 to obtain a memory address of a block in memory,
but does not teach translating high page 306 and, therefore, does not teach
translating the entirety of the most significant portion. Br. 4-5.
Appellants have persuaded us of Examiner error. We focus our
analysis on the contested claim language that requires using a translation
table “to translate the entirety of the most significant portion of the linear
address to obtain an address of a block of memory; . . .” (claim 1).
Davis teaches high page 306 and low segment 305 are inputs to XOR
gate 323, which results in a 12-bit output value {id. 147), that is combined
with the output binary values from base 321 and mask 322 (also using
bitwise OR gate 324) to form indexing address 325. Indexing address 325 is
further used as a pointer to select a page line entry 313 from page table 311
{id. 149). The selected page line entry 313 from page table 311 is further
processed by page line decode logic 326. The output of page line decode
logic 326 is used as an input to both selector 328 and comparator 327. Id.,
Fig. 3,11 50-56.
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Appeal 2016-005867
Application 13/785,188
Thus, high page 306 is used as an input in an address translation
process that eventually results in an indexing address 325 that is used as a
pointer “for selecting a page line 313 from base page table 311” in which
“indexing address 325 is the real address in memory of a page line 313 to be
accessed,” as depicted in page table 311. (Davis 147, Fig. 3).
As further described in Davis (1 56):
If the page line 313 is an EPTEG [(extended page table entry
group)], page line decode logic 326 provides a control signal to
that effect so that the page line passes directly to comparator 327
and selector 328. Selector 328 selects one 8-byte entry 401 [(Fig.
4)] in the EPTEG corresponding to the value of the 4 bits of low
page number 307 from the virtual address, and outputs the
corresponding real page number 402 [(Fig. 4)] from the selected
entry as the translated real page number 309.
(Emphasis added). In this manner, we find 4-bit low page 307 is merely
used as a control input to selector 328 to select one of 16 (0—15) inputs to
selector 328, and 12-bit high page 306 is not itself an input to selector 328.
Therefore, base page table 311 (the claimed “translation table”) is
used as part of a process to translate the 80-bit virtual address 301 to the 64-
bit real address 302, as depicted in Figure 3 of Davis. However, base page
table 311 (“translation table” — claim 1) is not used to translate the entirety
of the most significant portion (high page 306 and low page 307) of the
linear address, as required by claim 1, because low page 307 is merely used
as a direct control input to selector 328, i.e., low page 307 is not translated
by base page table 311. Moreover, high page 306 is not directly “translated”
by table 311, but is instead merely used to form part of an index address
(325) that is used to point to the contents of page line 313 in table 311.
We emphasize again the Examiner reads the recited “entirety of the
most significant portion of the linear address” (claim 1) on not just the 12-bit
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Appeal 2016-005867
Application 13/785,188
high page portion 306 considered alone, but also including the 4-bit low
page portion 307. See Final Act. 3.
Accordingly, on this record, Appellants have persuaded us the
Examiner has failed to establish Davis teaches or suggests “using the located
translation table to translate the entirety of the most significant portion of
the linear address to obtain an address of a block of memory,” as recited in
claim 1. (Emphasis added). We, therefore, do not sustain the obviousness
rejection of claim 1. We also do not sustain the rejections of claims 3-9,
which depend therefrom.
The Examiner provisionally rejects claims 1 and 3-9 on the ground of
nonstatutory double patenting as being unpatentable over claims 1, 3—7, 15,
and 17—24 of co-pending Application No. 13/517,758, in view of Davis. We
decline to reach the provisional rejection as the issues are not ripe for
decision. See Ex parte Moncla, 95 USPQ2d 1884, 1885 (BPAI 2010)
(precedential).
DECISION
We reverse the decision of the Examiner to reject claims 1 and 3-9.
REVERSED
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