10899808 (P.T.A.B. May. 30, 2014)

Ex Parte Buer

Patent Trial and Appeal BoardMay 30, 2014

10899808 (P.T.A.B. May. 30, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 10/899,808 07/27/2004 Mark Buer 3875.0110001 6999 26111 7590 05/30/2014 STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C. 1100 NEW YORK AVENUE, N.W. WASHINGTON, DC 20005 EXAMINER RUTZ, JARED IAN ART UNIT PAPER NUMBER 2187 MAIL DATE DELIVERY MODE 05/30/2014 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte MARK BUER ___________ Appeal 2011-012017 Application 10/899,808 Technology Center 2100 ____________ Before JOSEPH F. RUGGIERO, JEFFREY S. SMITH, and DANIEL N. FISHMAN, Administrative Patent Judges. FISHMAN, Administrative Patent Judge. DECISION ON APPEAL This is an appeal under 35 U.S.C. § 134(a) from the final rejection of all pending claims 1-3, 5, 9-14, 16, 18-31, and 38-45. Claims 4, 6-8, 15, 17, and 32-37 are cancelled. We have jurisdiction under 35 U.S.C. § 6(b). We affirm-in-part. Appeal 2011-012017 Application 10/899,808 2 STATEMENT OF THE CASE THE INVENTION Appellant’s invention relates to “sharing an external memory between functional modules of an integrated circuit chip.” Abstract. Claim 1 is illustrative: 1. A method of using an off-chip memory by an integrated circuit chip comprising: transmitting data through an on-chip data interface that is communicatively coupled to an on-chip internal data bus, said on-chip internal data bus communicatively coupled to a plurality of on-chip functional modules, said on-chip functional modules storing and retrieving data into and out of said off-chip memory by way of said on-chip data interface and said on-chip internal data bus, said off-chip memory used and shared by said plurality of on-chip functional modules by way of using said on-chip data bus to reduce the amount of off-chip memory required, said integrated circuit chip situated on a network interface card seated on a motherboard within a computer. THE REJECTIONS Claims 9-14, 16, 26, 27, and 31 are rejected under 35 U.S.C. § 112, first paragraph. Claims 1-3, 21, and 28-30 are rejected under 35 U.S.C. § 103(a) as unpatentable over Brooks (US 2001/0039600 A1), Runaldue (US 6,052,751), and McLean (US 6,128,658). Claims 44 and 45 are rejected under 35 U.S.C. § 103(a) as unpatentable over Brooks, Runaldue, and Stanaway (US 2002/0129271 A1). Claims 18-20 are rejected under 35 U.S.C. § 103(a) as unpatentable over Brooks, Runaldue, and Campbell (US 2003/0070010 A1). Appeal 2011-012017 Application 10/899,808 3 Claims 5, 23, and 24 are rejected under 35 U.S.C. § 103(a) as unpatentable over Brooks, Runaldue, McLean, and Rodgers (US 2003/0217322 A1). Claims 22 and 25 are rejected under 35 U.S.C. § 103(a) as unpatentable over Brooks, Runaldue, McLean, and Applicant’s Admitted Prior Art (“AAPA”). Claims 38, 40, and 41 are rejected under 35 U.S.C. § 103(a) as unpatentable over Darringer (J. A. Darringer et al., Early analysis tools for system-on-a-chip design, IBM J. Res. & Dev, pp. 691-707, 2002), Runaldue, and Campbell. Claim 39 is rejected under 35 U.S.C. § 103(a) as unpatentable over Darringer, Runaldue, Campbell, and AAPA. Claim 42 is rejected under 35 U.S.C. § 103(a) as unpatentable over Darringer, Runaldue, Campbell, and Rodgers. Claim 43 is rejected under 35 U.S.C. § 103(a) as unpatentable over Darringer, Runaldue, Campbell, and Stanaway. Rather than repeat all arguments here, we refer to Appellant’s Appeal Brief (“App. Br.” filed April 1, 2011), Appellant’s Reply Brief (“Reply Br.” filed July 12, 2011), and the Examiner’s Answer (“Ans.” mailed May 12, 2011) for the respective positions of Appellant and the Examiner. Arguments that Appellant did not make in the Briefs are deemed to be waived. See 37 C.F.R. § 41.37(c)(1)(vii). Appeal 2011-012017 Application 10/899,808 4 ANALYSIS SECTION 112 REJECTION The Examiner finds “said memory implemented within each of said first and said second on-chip functional modules” as recited in claim 9 is not supported by the Specification and thus claim 9 does not comply with the written description requirement of § 112, first paragraph. Ans. 32-34. Appellant argues originally filed claim 5, which is part of the original disclosure, supports this limitation by reciting “a one time programmable memory implemented within said one or more on-chip functional modules.” App. Br. 18; Reply Br. 9-10. We agree. Specifically, the description must “clearly allow persons of ordinary skill in the art to recognize that [the inventor] invented what is claimed.” In other words, the test for sufficiency is whether the disclosure of the application relied upon reasonably conveys to those skilled in the art that the inventor had possession of the claimed subject matter as of the filing date. Ariad Pharmaceutical, Inc. v. Eli Lilly and Co., 598 F.3d 1336, 1351 (Fed. Cir. 2010) (internal citations omitted). We construe claim 9 as requiring that each of the first and second functional modules includes a memory that provides one or more bits used in generating an identifier. We find originally filed claim 5 discloses that the inventor possessed the invention of claim 9 as we so construe claim 9. The Examiner explains that the recitations of claim 9 and originally filed claim 5 are not the same and interprets claim 9 as requiring “that the single memory is implemented within both of the first and second functional modules.” Ans. 33. It appears that the Examiner’s interpretation requires that a single memory is implemented in some distributed manner on both the first and second functional modules—an interpretation that is arguably not supported by the Appeal 2011-012017 Application 10/899,808 5 written description. We find the Examiner’s interpretation of claim 9 unreasonable in view of the Specification (including originally filed claim 5). In view of the above discussion, we do not sustain the Examiner’s § 112 rejection of claim 9 and its dependent claims 10-14, 16, 26, 27, and 31. SECTION 103 REJECTIONS We have reviewed the Examiner's rejections in light of Appellant’s arguments that the Examiner has erred. App. Br. 16-105; Reply Br. 5-93. Except as distinguished below, we agree with, and adopt as our own, the findings and reasons set forth by the Examiner in the action from which this appeal is taken (see Ans. 5-32) and as set forth by the Examiner in the Examiner’s Answer in response to Appellant’s Appeal Brief (see Ans. 34- 74). We highlight and address specific arguments and findings for emphasis as follows. REJECTION OF CLAIMS 1-3, 21, AND 28-30 CLAIM 1 Appellant argues the Examiner erred in rejecting independent claim 1 for a variety of reasons. App. Br. 21-30. We discuss the various issues raised in Appellant’s arguments below. Combinability of References Appellant argues “Brooks cannot be combined with Runaldue because Brooks teaches a cable modem while Runaldue teaches a multiport switch” Appeal 2011-012017 Application 10/899,808 6 and are therefore non-analogous art. App. Br. 21-22. Appellant further argues the components of Brooks and Runaldue are not interchangeable. App. Br. 21. Appellant further states: “Appellant respectfully disagrees that one of ordinary skill in the art knowledgeable in cable modems (Brooks) would be knowledgeable in the area of switches (Runaldue), and vice- versa.” App. Br. 22. We disagree. The Examiner explains Brooks and Runaldue are in the same field of endeavor—design of network devices (Ans. 7) and “[b]oth Brooks and Runaldue teach an integrated circuit for receiving, processing, and transmitting packets of data over transmission media.” Ans. 34. The Examiner further explains: Further, the Examiner respectfully notes that, as per MPEP 2145(III): “The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference . . . Rather, the test is what the combined teachings of those references would have suggested to those of ordinary skill in the art.” In re Keller, 642 F.2d 413, 425, 208 USPQ 871, 881 (CCPA 1981). See also In re Sneed, 710 F.2d 1544, 1550,218 USPQ 385,389 (Fed. Cir. 1983) (“[I]t is not necessary that the inventions of the references be physically combinable to render obvious the invention under review.”); and In re Nievelt, 482 F.2d 965, 179 USPQ 224, 226 (CCPA 1973) (“Combining the teachings of references does not involve an ability to combine their specific structures.”). Ans. 35. We agree. Appellant’s arguments improperly seek bodily, physical integration of the circuits and logic of Brooks and Runaldue. Appellant similarly argues McLean is non-analogous art and thus not properly combined with Brooks and Runaldue and further contends the Examiner has provided no evidence to support a motivation to combine McLean with Brooks and Runaldue. App. Br. 26-28. The Examiner finds Appeal 2011-012017 Application 10/899,808 7 McLean, Brooks, and Runaldue are all in the related art of networking devices. Ans. 41. We agree. The Examiner further explains that Brooks is relied on for teaching an integrated circuit on a network interface (i.e., a single circuit forming an internal modem). Ans. 39 (citing Brook ¶¶ 0024, 0025). McLean is relied on for teaching exchange of wake-up messages via network interface cards (“NICs”) that may be inserted in PCI slots of respective computer systems. Ans. 39 (See, e.g., McLean Abstract; Figs. 1, 2). Thus, the Examiner finds: Examiner respectfully submits that as Brooks teaches that device 100 may be a single integrated circuit in an internal modem, and McLean teaches that NICs may be connected to a motherboard by PCI slots It would have been obvious to embody an integrated circuit based on the teachings of Brooks and Runaldue on a network interface card seated on a motherboard within a computer as recited in claim 1. Ans. 39-40. We agree. On-Chip Interface and Data Bus Appellant argues Runaldue fails to teach storing and retrieving data in an off-chip memory “by way of said on-chip data interface and said on-chip internal data bus.” App. Br. 23-24. Appellant particularly argues there is no on-chip internal data bus disclosed in Runaldue. Id. at 24. We disagree. The Examiner correctly explains Appellant’s argument improperly attacks the references separately while the rejection is based on the combined teachings of the references. Ans. 38 (see, e.g., Keller at 426; see also In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986)). The Examiner further explains Brooks teaches “a plurality of functional modules connected to an off-chip memory by way of an on-chip interface and data Appeal 2011-012017 Application 10/899,808 8 bus, which is shown in figure 2” and “Runaldue, at column 1 lines 13-16 shows that the invention is directed to controlling access to a memory by a plurality of busses.” Id. The Examiner, therefore, finds Runaldue (in combination with Brooks) teaches the disputed limitation “by way of said on-chip data interface and said on-chip internal data bus,” as recited in claim 1. We agree. IC on a Network Interface Card Appellant argues McLean fails to teach an “integrated circuit chip situated on a network interface card,” as recited in claim 1. App. Br. 25. We disagree. The Examiner again notes the Appellant improperly attacks the references separately. Ans. 39. We agree. The Examiner explains Brooks discloses a device implemented as a single integrated circuit that can be implemented as an internal modem. Id. (citing Brooks ¶¶ 0024, 0025). The Examiner further explains it is well known that such an internal modem may be constructed on an expansion card to be installed in the slots of a computer motherboard. Id. (citing the Microsoft Computer Dictionary as evidence that such a structure is well known). Furthermore, the Examiner explains that McLean discloses this well-known design as a NIC that may be inserted in a PCI slot of the computer system. Id. The Examiner then finds it would be obvious in view of these combined teachings to “embody an integrated circuit based on the teachings of Brooks and Runaldue on a network interface card seated on a motherboard within a computer as recited in claim 1.” Id. at 39-40. We agree. Appeal 2011-012017 Application 10/899,808 9 Reduce Amount of Off-Chip Memory Appellant argues Runaldue does not teach “using said on-chip data bus to reduce the amount of off-chip memory required,” as recited in claim 1. App. Br. 28-29. We disagree. The Examiner explains the recitation “‘to reduce the amount of off-chip memory required’ is a statement of the purpose of using the on-chip data bus, and does not result in a structural or functional difference in the claimed invention.” Ans. 43. In other words, the recitation is merely an intended purpose and hence need not be afforded patentable weight in determining patentability over the prior art. We agree. “An intended use or purpose usually will not limit the scope of the claim because such statements usually do no more than define a context in which the invention operates.” Boehringer Ingelheim Vetmedica, Inc. v. Schering- Plough Corp., 320 F.3d 1339, 1345 (Fed. Cir. 2003). Moreover, a “clause in a method claim is not given weight when it simply expresses the intended result of a process step positively recited.” Minton v. Nat'l Ass'n of Securities Dealers, Inc., 336 F.3d 1373, 1381 (Fed. Cir. 2003) (citation omitted). We agree. Even presuming the intended purpose is deserving of consideration in distinguishing the invention over the art, the Examiner explains that Runaldue teaches use of the on-chip data bus to store data in both on-chip memory and off-chip memory and hence concludes, “As part of the data is stored in the on-chip memory, less off-chip memory is required to store the queued data, as part of it is in the on-chip memory [(thus reducing the amount of off-chip memory)].” Ans. 42. We agree. Appeal 2011-012017 Application 10/899,808 10 Functional Modules Appellant argues Runaldue’s buffer manager 72, rules checkers 42 and 58, and FIFO 52 are not functional modules that store and retrieve data in the off-chip memory as recited in claim 1. App. Br. 29-30. We disagree. The Examiner again notes the Appellant improperly attacks the references separately. Ans. 43. We agree. Regardless, the Examiner relies on Brooks for disclosing a plurality of functional modules connected to internal busses 210 and 214 that, in turn, connect the functional modules to DRAM interface 124. Ans. 5 (citing Brooks Fig. 2; ¶¶ 0027, 0032). The Examiner also relies on Runaldue as showing functional modules that store and retrieve data in an off-chip memory. Ans. 6 (citing Runaldue Fig. 2; col. 5, l. 58 through col. 6, l. 7; col. 6, ll. 43-56). The Examiner further explains that Runaldue column 7, lines 50-53 shows that data is transferred over the internal data bus from the receive FIFO to an off-chip memory in a DMA transaction and explains Brooks figure 4 and paragraphs 0054-0061 discuss multiple functional modules that exchange data using various queues (i.e., memory). Ans. 43-44. We agree. We find Appellant’s arguments in the Reply Brief (Reply Br. 10-29) are not persuasive to rebut the Examiner’s rejection and responses regarding the arguments relating to claim 1. We are, therefore, not persuaded that the Examiner has erred in rejecting claim 1. CLAIM 2 Claim 2 depends from claim 1 and further recites a particular use of a bus arbiter in the integrated circuit. Appellant argues the Examiner erred in rejecting claim 2 because, although Brooks paragraph 0039 discloses a bus Appeal 2011-012017 Application 10/899,808 11 arbiter that controls access to a bus, Brooks does not disclose arbitrating storage and retrieval between the functional modules and the off-chip memory as claimed. App. Br. 32. We disagree. The Examiner explains arbiter 218 of Brooks “must arbitrate what device has access to the bus in order for the DRAM interface, and therefore the off-chip memory, to be accessed.” Ans. 44. We agree and find Appellant does not persuasively rebut the Examiner’s explanation. See Reply Br. 31. We, therefore, are not persuaded that the Examiner erred in rejecting claim 2. CLAIM 3 Claim 3 depends from claim 1 and further recites particular use of an identifier in data blocks read and written in the off-chip memory. Appellant argues the Examiner erred in rejecting claim 3 because, Runaldue’s teachings of source and destination MAC addresses in Ethernet protocol packets that are used by rules checkers does not teach “writing and reading one or more data blocks into said off-chip memory, wherein each of said one or more data blocks is identified using an identifier, said identifier used for identifying a data block required by one of said plurality of on-chip functional modules,” as recited in claim 3. App. Br. 34-35. We disagree. The Examiner explains Runaldue teaches Ethernet packets having MAC addresses are written to, and read from the off-chip memory and that rules checkers use the destination MAC address of a packet to determine the output port of the packet. Ans. 45. We agree and, therefore, find Runaldue teaches or suggests an identifier (MAC address) that identifies the data block (Ethernet packet) as required by a functional module (rules checker). We further find Appellant does not persuasively Appeal 2011-012017 Application 10/899,808 12 rebut the Examiner’s explanation. See Reply Br. 33-34. We, therefore, are not persuaded that the Examiner erred in rejecting claim 3. CLAIMS 28 AND 29 Independent claim 28 is an apparatus claim analogous to method claim 1 but specifically recites “one or more control processors resident within said one or more functional modules, said one or more control processors used to control or arbitrate access to said off-chip memory by way of communicating through said internal data bus.” The Examiner rejects claim 28 for the essentially same reasons as claims 1 and 2. Ans. 10-12. Appellant argues the Examiner erred in rejecting claim 28 for essentially the same reasons as claims 1 and 2 (App. Br. 38-43) and, for essentially the same reasons discussed supra regarding claims 1 and 2, we are not persuaded of Examiner error. Appellant further argues Brooks paragraph 0039 fails to teach the above limitation of claim 28. App. Br. 43-46. Specifically, Appellant argues processors 102 and 104 of Brooks’ figure 2 “are not within any functional module.” App. Br. 45. We disagree. The Examiner explains processors 102 and 104 are functional modules in that they perform functions and, as functional modules, are resident within one or more functional modules as claimed. Ans. 49. We agree. The Specification provides no specific definition of “functional module” or what it means to be resident within such a module. Thus, we find the Examiner’s interpretation of “one or more control processors resident within said one or more functional modules” as reading on Brooks’ processors 102 and 104 is broad but reasonable and consistent Appeal 2011-012017 Application 10/899,808 13 with the Specification. We further find Appellant does not persuasively rebut the Examiner’s explanation. See Reply Br. 34-42. We, therefore, are not persuaded that the Examiner erred in rejecting claim 28. Dependent claim 29 (dependent from claim 28) is rejected for reasons similar to claims 2 and 28 and Appellant presents essentially identical arguments. App. Br. 46; Reply Br. 41-42. For the same reasons as claims 2 and 28, discussed supra, we are not persuaded the Examiner erred in rejecting claim 29. Appellant does not separately argue claims 21 and 30. App. Br. 29, 46. In view of the above discussion, we sustain the Examiner’s decision rejecting claims 1-3, 21, and 28-30. REJECTION OF CLAIMS 44 AND 45 Independent method claim 44 and independent apparatus claim 45 are similar to claims 1 and 28, respectively, but each includes the limitation, “said plurality of functional modules comprising a functional module that performs authentication of a user of said computer.” The Examiner rejects both claims for essentially the same reasons as claims 1 and 28 (Ans. 15-18) and further relies on Stanaway for teaching the additional limitation as “the use of a security gateway (item 111) which performs user authentication (see paragraph 0018).” Ans. 15, 17. The Examiner further explains Stanaway discloses use of “‘[a]n authentication protocol such as RADIUS is then performed to authenticate the user’s access.’” Ans. 51 (quoting Stanaway ¶ 0018). The Examiner then finds, “By sending the first packet, the network Appeal 2011-012017 Application 10/899,808 14 device from which the packet is sent is authenticating the user to the security gateway 111.” Id. Appellant contends: [T]he transmission of a data packet does not perform any such authentication of a user. The transmission of a data packet may provide identifying information such as user name, but the presence of information such as a user name does not necessarily mean that authentication has occurred or will occur. Reply Br. 44. We agree. The mere presence of user login information in a transmitted packet, without more, does not necessarily teach or suggest that an “authentication of a user of said computer” is performed as claimed. Though the Examiner indicates that the RADIUS protocol is used to perform such authentication, the Examiner does not indicate how Stanaway teaches that the RADIUS protocols authenticate the user of the computer since Stanaway is directed authenticating usage of a virtual private network (“VPN”). See, e.g., Stanaway Abstract. Therefore, on the record before us, we do not sustain the Examiner’s decision rejecting claims 44 and, for the same reasons, claim 45. REJECTION OF CLAIMS 18-20 Independent method claim 18 is similar to claims 1 and 2 but includes the limitation, “said plurality of functional modules implemented in an integrated circuit chip on a motherboard within a computer.” The Examiner rejects claim 18 for essentially the same reasons as claims 1 and 2 (Ans. 18-21) but further relies on Campbell for teaching the additional limitation (Ans. 20-21). Appellant argues the Examiner erred in rejecting claim 18 for essentially the same reasons as claims 1 and 2 (App. Br. 63-77) and, for Appeal 2011-012017 Application 10/899,808 15 essentially the same reasons discussed supra regarding claims 1 and 2, we are not persuaded of Examiner error. Appellant further argues “Campbell discloses a ‘network interface card (NIC) or LAN on motherboard (LOM).’ Therefore, there is no disclosure of a ‘network interface circuit’ as alleged by the Examiner. Appellant submits that a ‘card’ on a motherboard does not teach an ‘integrated circuit chip’ on a motherboard.” App. Br. 71. We disagree. Again as discussed supra, Appellant’s argument attacks the references separately while the rejection is based on the combined teachings of the references. The Examiner explains that Brooks is relied on to teach that the functional modules may be implemented within a single integrated circuit (Ans. 19, 59) and Campbell is relied on merely for showing such an integrated circuit could be a LAN on a motherboard (“LOM”) is well known. Ans. 59-61. We agree and further find Appellant’s reply fails to persuasively rebut the Examiner’s findings. See Reply Br. 57-65. In view of the above discussion, we are not persuaded the Examiner erred in rejecting claim 18. Claim 19 depends from claim 18 and further recites a bus arbiter similar to claim 2. Appellant argues Brooks fails to disclose the arbitration features for essentially the same reasons as claim 2 supra and, for essentially the same reasons as claim 2, we are not persuaded the Examiner erred in rejecting claim 19. In view of the above discussion, we sustain the Examiner’s decision rejecting claims 18 and 19 as well as claim 20 not separately argued by Appellant (App. Br. 71). Appeal 2011-012017 Application 10/899,808 16 REJECTION OF CLAIMS 5, 23, AND 24 Claim 5 depends from claim 3 and further recites “said identifier is generated by way of a one time programmable [(“OTP”)] memory implemented within a functional module.” The Examiner rejects claim 5 for the same reasons as claim 3 further in view of Rodgers for teaching the additional limitation. Ans. 22-23. Appellant argues the Examiner has erred in rejecting claim 5 by improperly characterizing Rodgers as storing a MAC address for a NIC (a MAC address being read by the Examiner as the recited identifier) and contends, “Instead, Rodgers discloses storing a network interface identifier code and information relating to the MAC address for the network interface.” App. Br. 82. We disagree. The Examiner explains the skilled artisan “would recognize that the network interface identifier code . . . is a MAC address.” We agree and also find “information relating to the MAC address” teaches or at least suggests that the MAC address is stored in the OTP and thus generated by the OTP. Appellant further argues the Examiner has erred in relying on Rodgers paragraph 0007 as motivation for combining Rodgers with Brooks, Runaldue, and McLean because Rodgers does not disclose anything about a MAC address. App. Br. 82. We disagree. The Examiner explains Rodgers paragraph 0007 teaches network cards “‘also require identification that is stored in this manner’” and that the skilled artisan knows that under a MAC address is a standard Appeal 2011-012017 Application 10/899,808 17 identifier for a network station (i.e., for a network card used in a network device). Ans. 64. We agree. We find Appellant’s reply does not persuasively rebut the Examiner’s explanations. See Reply Br. 66-72. Appellant presents no argument regarding the rejection of claim 23 which depends from claim 5. Claim 24 depends from claim 23 and further recites “each of said one or more identifiers is generated by processing said one or more bits by a logic circuitry [(as recited in claim 23)].” Appellant argues the Examiner erred in rejecting claim 24 because Rodgers’ read logic generates a read signal that causes further OTP processing but does not teach the limitation of claim 24. App. Br. 83. We disagree. The Examiner quotes the entirety of Rodgers paragraph 0043 and explains, “Rodgers shows that significantly more processing is performed on the bits read out from the OTP memory . . . than . . . argued by Applicant” and thus, concludes Rodgers teaches the limitation of claim 24. Ans. 65-66. We agree. We further find Appellant’s reply does not persuasively rebut the Examiner’s explanation. See Reply Br. 74. In view of the above discussion, we sustain the Examiner’s decision rejecting claims 5 and 24 and summarily sustain the Examiner’s decision rejecting claim 23. REJECTION OF CLAIMS 22 AND 25 Claims 22 and 25 depend from claim 1 and additionally recite that the off-chip memory a non-volatile memory and a non-volatile flash memory, respectively. The Examiner rejects these claims for the same reasons as Appeal 2011-012017 Application 10/899,808 18 claim 1 further combining AAPA (Spec. ¶ 06) for teaching the additional limitation. Ans. 23-24. Appellant argues Brooks, Runaldue, and McLean are not combinable for the same reasons as claim 1 (App. Br. 85-87) and for the same reasons as claim 1 supra, we are not persuaded of Examiner error. Appellant also similarly argues AAPA is non-analogous art and thus not combinable with Brooks, Runaldue, and McLean. App. Br. 87-88. We disagree. Specification paragraph 06 clearly relates to network interfaces disclosing that “The media access controller may, for example, require flash memory [(a form of non-volatile memory)] to store program code, MAC addresses, and other information or descriptors.” Thus, we find AAPA is clearly in the same field of endeavor as Brooks, Runaldue, and McLean—namely network device designs. See Ans. 66-67 (referring to earlier responses at Ans. 34-37). We further find Appellant’s reply does not persuasively rebut the Examiner’s explanation. See Reply Br. 75. In view of the above discussion, we sustain the Examiner’s decision rejecting claims 22 and 25. REJECTION OF CLAIMS 38, 40, AND 41 Independent claim 38 recites an integrated circuit similar to that of claim 28 and is rejected over Darringer, Runaldue, and Campbell. Ans. 24-27. Appellant argues the Examiner erred in that Darringer fails to teach the recited data interface for coupling the integrated circuit to an off-chip memory. App. Br. 91. We disagree. The Examiner explains Darringer teaches an “SDRAM- DDR controller core” that couples with an external memory (i.e., an off-chip Appeal 2011-012017 Application 10/899,808 19 memory) as well as another SDRAM controller core that couples with an on- chip memory. Ans. 67-68. We agree. Appellant argues, as above, the Examiner erred because Runaldue does not teach an off-chip memory shared by the functional modules. App. Br. 91. For the same reasons discussed supra, we are not persuaded the Examiner erred. Similar to arguments above, Appellant further argues the Examiner erred because Darringer, Runaldue, and Campbell are non-analogous prior art, and thus not combinable, because Darringer “relates to analysis tools for any system on a chip design” while Runaldue relates to network devices. App. Br. 92. We disagree. The Examiner explains Darringer relates to any system of a chip design and Runaldue is an example of a system on a chip for network communications. Ans. 69. Thus, we find the reference are in the same field of endeavor or at least pertinent to the problems addressed by Appellant’s invention. The Examiner further explains Darringer expressly discusses “an integrated circuit to perform packet forwarding, [i.e.,] a network device.” Id. We agree. Appellant argues, as above, the Examiner erred because Runaldue’s queues (FIFOs) are not functional modules that share access to the off-chip memory. App. Br. 93. As above, the Examiner explains Runaldue’s FIFOs, buffer manager, and rules checkers access packets in the off-chip memory that include MAC addresses and thus are functional modules as claimed. Ans. 70. Thus, for the same reasons supra, we are not persuaded the Examiner erred. Appeal 2011-012017 Application 10/899,808 20 We further find Appellant’s reply does not persuasively rebut the Examiner’s explanations (see Reply Br. 88-93) and we are, therefore, not persuaded the Examiner erred in rejecting claim 38. Appellant does not separately argue claim 40 (dependent from claim 38). App. Br. 93. Claim 41 depends from claim 38 and recites additional limitations similar to claim 3 discussed supra and, for essentially the same reasons as claims 3 and 38, we are not persuaded the Examiner erred in rejecting claim 41. In view of the above discussion, we sustain the Examiner’s decision rejecting claims 38, 40, and 41. REJECTION OF CLAIM 39 Claim 39 depends from claim 38 and recites additional limitations similar to claim 25 discussed supra and for essentially the same reasons we are not persuaded the Examiner erred in rejecting claim 39. We, therefore, sustain the Examiner’s decision rejecting claim 39. REJECTION OF CLAIM 42 Claim 42 depends from claim 41 and recites additional limitations similar to claim 24 discussed supra and for essentially the same reasons we are not persuaded the Examiner erred in rejecting claim 42. We, therefore, sustain the Examiner’s decision rejecting claim 42. REJECTION OF CLAIM 43 Claim 43 depends from claim 38 and recites additional limitations similar to the authentication features of claims 44 and 45 discussed supra and for essentially the same reasons we are persuaded the Examiner erred in Appeal 2011-012017 Application 10/899,808 21 rejecting claim 43. We, therefore, do not sustain the Examiner’s decision rejecting claim 43. DECISION For the above reasons, the Examiner’s decision rejecting claims 9-14, 16, 26, 27, and 31 under 35 U.S.C. §112, first paragraph is reversed.1 For the above reasons, the Examiner’s decision rejecting claims 43-45 under 35 U.S.C. § 103(a) is reversed. For the above reasons, the Examiner’s decision rejecting claims 1-3, 5, 18-25, 28-30, and 38-42 under 35 U.S.C. § 103(a) is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED-IN-PART ke 1 Should this application proceed with further prosecution, we suggest the Examiner consider whether any of claims 9-14, 16, 26, 27, and 31 are patentable under §§ 102 and 103 over, at least, the prior art of record. Furthermore, we note claims 26 and 27 purport to claim a method but depend (directly or indirectly) from claim 14 which recites a system. We suggest the Examiner consider whether claims 26 and 27 are patentable under 35 U.S.C. § 112, fourth paragraph.