Ex Parte Brunsilius et al

Patent Trial and Appeal Board

Mar 29, 2016

12902896 (P.T.A.B. Mar. 29, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/902,896 10/12/2010
79338 7590 03/31/2016
KENYON & KENYON LLP
1500 K STREET, NW
WASHINGTON, DC 20005-1257
FIRST NAMED INVENTOR
Janet M. BRUNSILIUS
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
13641/361402 2899
EXAMINER
TRA, ANH QUAN
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
03/31/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
uspto@kenyon.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte JANET M. BRUNSILIUS, STEPHEN R. KOSIC, and
COREY D. PETERSEN
Appeal2014-006359
Application 12/902,896
Technology Center 2800
Before CARL W. WHITEHEAD JR., JON M. JURGOV AN, and
AARON W. MOORE, Administrative Patent Judges.
JURGOVAN, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 seek review under 35 U.S.C. § 134(a) from a Final
Rejection of claims 16, 22-26, 28, 30-32, and 36-42, the only claims
pending in this application. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse. 2
1 Appellants identify Analog Devices, Incorporated as the real party in
interest. App. Br. 2.
2 Our Decision refers to the Specification (filed Oct. 12, 2010) ("Spec."); the
Final Office Action (mailed July 19, 2013) ("Final Act."); the Appeal Brief
(filed Jan. 17, 2014) ("App. Br."); the Examiner's Answer (mailed Mar. 6,
2014) ("Ans."); and the Reply Brief (filed May 2, 2014) ("Reply Br.").
Appeal2014-006359
Application 12/902,896
STATEMENT OF THE CASE
The claims are directed to a switch circuit including an NMOS
transistor with an n-well connected to a diode to provide voltage to then-
well selectively based on the state of a switch signal applied to the
transistor's gate. (Spec., Abstract.) Claim 38, reproduced below, is
illustrative of the claimed subject matter:
38. A switch circuit, comprising:
an NMOS transistor, including:
a source to receive an input signal, a gate to receive
a first switching signal, and a drain to provide the input
signal, after passing through the NMOS transistor, as an
output signal during an enable phase of the first switching
signal;
a p-well containing the drain and the source;
an n-well under the p-well; and
a diode having a cathode terminal connected to then-well
and an anode terminal connected to a circuit node that receives
one of an upper supply voltage and a boosted voltage higher than
the upper supply voltage, wherein the diode passively turns off
during the enable phase of the first switching signal.
REJECTIONS
Claim 38 stands rejected under 35 U.S.C. § 103(a) based on Shigehara
(US 6,335,653 Bl; iss. Jan. 1, 2002); Yamauchi (US 6,373,321; iss. Apr. 16,
2002); and Koga (US 6,191,615 Bl; iss. Feb. 20, 2001). (Final Act. 2-3.)
Claims 16, 22-25, 28, 30-32, 36, 37, and 39--42 stand rejected under
35 U.S.C. § 103(a) based on Shigehara; Yamauchi; Koga; and Tu (US
7,724,067; iss. May 25, 2010). (Final Act. 3---6.)
Claim 26 stands rejected under 35 U.S.C. § 103(a) based on Tsugai
(US 5,986,497; iss. Nov. 16, 1999); Shigehara; Yamauchi; Koga; and Tu.
(Final Act. 6-7.)
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Appeal2014-006359
Application 12/902,896
ANALYSIS
Claim 38
Appellants argue, inter alia, that Shigehara's and Yamauchi's
transistor substrates are distinct from the disclosed n-wells, and there is no
teaching or suggestion to modify Koga's Figure 5 circuit and apply it to a
transistor's n-well as opposed to a substrate (App. Br. 9). Because we agree
with Appellants on this argument, we do not address the remaining
arguments.
Specifically, we agree with Appellants that the Examiner has pointed
to no teaching or suggestion to modify Koga's circuit to extract the diode
and connect it to then-wells of Shigehara's or Yamauchi's circuits. Instead,
it appears the Examiner has engaged in impermissible hindsight reasoning in
which Appellants' own teachings are used against them in the rejection. It is
well recognized that "[ o ]bviousness may not be established using hindsight
or in view of the teachings or suggestions of the inventor." Para-Ordnance
klfg., Inc. v. SGS Importers Int 'l, Inc., 73 F.3d 1085, 1087 (Fed. Cir. 1995)
(citing W.L. Gore & Assocs., Inc. v. Garlock, Inc., 721F.2d1540, 1551,
1553 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984)). In addition, "[i]t
is impermissible to use the claimed invention as an instruction manual or
'template' to piece together the teachings of the prior art so that the claimed
invention is rendered obvious." In re Fritch, 972 F.2d 1260, 1266 (Fed. Cir.
1992) (citing In re Gorman, 933 F.2d 982, 987 (Fed. Cir. 1991)).
The Examiner indicates it would have been obvious to use Koga's
circuit of Figure 5 to generate Vpp for Shigehara's Figure 11 circuit as
modified by Yamauchi Figure 2A for the purpose of saving space and cost.
(Final Act. 2-3.) No further explanation is given to explain why a person of
ordinary skill would combine Koga with the Shigehara-Yamauchi modified
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Appeal2014-006359
Application 12/902,896
circuit. In fact, contrary to the Examiner's conclusory finding, it appears
that adding Koga' s diode to the Shigehara-Yamauchi modified circuit may
well require additional space and cost. Accordingly, we are not persuaded
saving space and cost is a viable reason to combine Koga with Shigehara
and Yamauchi in the§ 103(a) rejection. Thus, we find Appellants'
argument to be persuasive.
Claims 16, 22-25, 28, 30--32, 36, 37, and 39--42
Appellants present similar arguments against the§ 103(a) rejection of
the stated claims based on Shigehara, Yamauchi, Koga, and Tu. (App. Br.
11-12.) The Examiner relies on Tu to teach a switching circuit using non-
overlapping signals. (Final Act. 3.) Because the cited part of Tu does not
teach or suggest the deficiencies of the other cited references relative to
claim 16, we do not sustain the rejection.
Specifically, claim 16 recites a diode connected to an n-well of an
NMOS transistor. We agree with Appellants that there is no cited evidence
providing a reason to extract Koga's diode from its Figure 5 circuit and
connect it with then-well of the Shigehara-Yamauchi modified circuit. Tu
likewise fails to provide any reason to combine the references. Accordingly,
the Examiner has engaged in impermissible hindsight by using Appellants'
own teachings against them in the§ 103(a) rejection. See Para-Ordnance,
W.L. Gore, Fritch, Gordon, supra. Thus, we do not sustain the rejection of
claim 16 or the rejection of claim 38, which is commensurate in scope.
The remaining claims depend from either claim 16 or claim 38. For
the reasons previously stated with respect to claim 16 and claim 38, we do
not sustain the rejection of claims 22-25, 28, 30-32, 36, 37, and 39--42
under§ 103(a).
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Appeal2014-006359
Application 12/902,896
Claim 26
Appellants present similar arguments against the§ 103(a) rejection of
claim 26 based on Tsugai, Shigehara, Yamauchi, Koga, and Tu. (App. Br.
12.) The Examiner relies on Tsugai to teach an NMOS transistor with a
capacitor connected as claimed. (Final Act. 6-7.) Tsugai actually shows a
capacitor connected to an operational amplifier, not an NMOS transistor.
(See Tsugai Fig. 1.) Accordingly, Tsugai does not overcome the rejection
deficiencies noted with respect to claim 16, from which claim 26 depends.
Thus, we are persuaded of error in the rejection of claim 26 under§ 103(a)
for the reasons previously stated.
DECISION
For the above reasons, the Examiner's rejections of claims 16, 22-26,
28, 30-32, and 36-42 under§ 103(a) are reversed.
REVERSED
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