Ex Parte Brown et al

Patent Trial and Appeal Board

Aug 30, 2013

11468838 (P.T.A.B. Aug. 30, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/468,838 08/31/2006 David A. Brown Brown 16-14-41-1 5609
7590 08/30/2013
Ryan, Mason & Lewis, LLP
90 Forest Avenue
Locust Valley, NY 11560
EXAMINER
NGUYEN, STEVE N
ART UNIT PAPER NUMBER
2117
MAIL DATE DELIVERY MODE
08/30/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte DAVID A. BROWN, JAMES THOMAS KIRK,
DAVID P. SONNIER, and CHRIS R. STONE

____________

Appeal 2011-004357
Application 11/468,838
Technology Center 2100
____________

Before JOSEPH L. DIXON, ST. JOHN COURTENAY III, and
CARLA M. KRIVAK, Administrative Patent Judges.

COURTENAY, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2011-004357
Application 11/468,838

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STATEMENT OF THE CASE
The Examiner finally rejected claims 1-8, 10, 12-22, and 24-30.
Claims 9, 11, and 23 were canceled. (App. Br. 2). Appellants appeal
therefrom under 35 U.S.C. § 134(a). We have jurisdiction under 35 U.S.C.
§ 6(b).
We affirm.

INVENTION
This invention "relates to techniques for enhancing the yield of
manufacturing [electronic] devices by means of improved failure analysis."
(Spec. 1).1 Claim 1, reproduced below, is representative of the claimed
subject matter:
1. In a system including a processor and memory coupled to the
processor, a method of device failure analysis, the method
comprising the steps of:
[a] upon each error detected within a test series performed on a
device, the processor storing within a table in the memory an
address at which the error occurred in the device and storing a
bit position of each failed bit corresponding to that address;
[b] for each unique address at which at least one error occurred,
determining how many different bit positions corresponding to
the address failed during the test series; and

1 See exemplary “devices” as described in the Specification: “A ‘device’ as
the term is used herein may comprise, by way of example and without
limitation, elements such as those commonly associated with an application-
specific integrated circuit (ASIC), single inline memory module (SIMM),
dual inline memory module (DIMM), content-addressable memory (CAM),
central processing unit (CPU), digital signal processor (DSP), or any other
type of data processing or storage device, as well as portions and/or
combinations of such elements.” (Spec. 4, ll. 13-18, emphasis added).
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[c] declaring the device to have failed the test series when the
number of failed bit positions for at least a given address
exceeds a number of allowable bit errors per address such that
at least one failed bit is uncorrectable.
(Steps lettered and disputed limitation emphasized).
REJECTIONS
R1. Claims 1-5, 7, 8, 10, 12-22, and 24-30 stand rejected under 35
U.S.C. §103(a) as unpatentable over U.S. Patent No. 6,029,260
("Hashizume") and U.S. Patent No. 6,574,757 ("Park").
R2. Claim 6 stands rejected under 35 U.S.C. §103(a) as unpatentable
over Hashizume and Park in view of U.S. Patent No. 6,157,558 ("Wong").

GROUPING OF CLAIMS
Based on Appellants' arguments, we decide the appeal of the
obviousness rejection R1 of independent claims 1, 17, 26, and 27 and
dependent claims 2-5, 10, 12-16, 18-22, and 24 and on the basis of claim 1.
(App. Br. 8). See 37 C.F.R. § 41.37(c)(1)(iv).
Based on Appellants' arguments, we decide the appeal of the
obviousness rejection R1 of claims 7 and 8 on the basis of claim 7. See Id.
Based on Appellants' arguments, we decide the appeal of the
obviousness rejection R1 of claims 28-30 on the basis of claim 28. See Id.
Based on Appellants' arguments, we decide the appeal of the
obviousness rejection R1 of claim 25 separately, infra.
We address the obviousness rejection R2 of claim 6 separately, infra.

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Application 11/468,838

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ANALYSIS
We disagree with Appellants’ contentions regarding the Examiner’s
obviousness rejections of the claims. We adopt as our own: (1) the findings
and reasons set forth by the Examiner in the action from which this appeal is
taken, and (2) the reasons set forth by the Examiner in the Answer in
response to arguments made in Appellants’ Appeal Brief. (Ans. 17-19). We
highlight and address specific findings and arguments below.
R1.
INDEPENDENT CLAIMS 1, 17, 26, AND 27
Issue: Under § 103, did the Examiner err in finding the
cited references, either alone or in combination, would have
taught or suggested "declaring the device to have failed the test
series when the number of failed bit positions for at least a
given address exceeds a number of allowable bit errors per
address such that at least one failed bit is uncorrectable," within
the meaning of claim 1 and the commensurate language of
claims 17, 26, and 27?
Appellants contend:
However, the cited portions of Hashizume make clear
that the determination of whether or not defective cells can be
remedied by the use of remedy lines is not based on a number
of failed bit positions for a given address, but rather are based
on whether a surplus remedy line is available. Whether a
surplus remedy line is available in tum depends on how many
remedy lines have been used compared with how many remedy
lines are provided. See, for example, Hashizume at column 9,
lines 11-27, with reference to FIGS. 9-11. Note that the
arrangements shown in FIGS. 9 and 11 both include a row
having five failed bits, yet the former can be corrected using
remedy lines while the latter cannot.
(Reply Br. 2 (emphasis added); see also App. Br. 9-10).
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Appellants' contention that Hashizume's device failure is not based on
a number of failed bit positions for a given address, but rather is based on
whether a surplus remedy line is available is not persuasive. (Id.) This is
because the number of surplus remedy lines available at a given time is a
determinable number, as is the "number of failed bit positions for at least a
given address." (Ans. 17-18). Therefore, Hashizume's device failure is
declared based on "the number of failed bit positions for at least a given
address." (Id.). For example, for the embodiment shown in Hashizume's
Figure 11, for given address 6 (Row 6), there are no surplus remedy lines,
two failed bit positions (F9, F11), and one is the "number of allowable bit
errors per address." (See Figs. 10 and 11; col. 9, l. 21-27; first defect F9 is
allowable, second defect F11 is not allowable). Furthermore, the limitation
"number of allowable bit errors per address" does not require all addresses to
have the same "number of allowable bit errors per address."
Moreover, we find the limitation at issue would have also been taught
or suggested by Hashizume's background description of a prior art device
having no error correction. (Col. 1, ll. 10-16). Thus, we find Hashizume's
device without error correction (id.) is declared to have failed "the test series
when the number of failed bit positions for at least a given address exceeds"
[zero] "a number of allowable bit errors per address such that at least one
failed bit is uncorrectable." (Claim 1). We conclude the plain language of
claim 1 does not require any error correction, thus the "number of allowable
bit errors per address" can be zero and any error fails the device. (Id.).
For these reasons, on this record, we are not persuaded of Examiner
error. Accordingly, we sustain the Examiner's rejection of independent
claim 1 and claims 2-5, 10, 12-22, 24, and 26-27, which fall therewith.
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CLAIMS 7-8
Regarding claim 7's limitation of "declaring the device to have failed
the test series when the number of errors detected within the test series
exceeds a threshold of allowable errors," Appellants contend Hashizume's
maximum correctable errors capacity would not have taught or suggested the
claimed "threshold of allowable errors" because Hashizume's maximum
correctable errors capacity is related to available surplus remedy lines, which
is related to the locations of the failed bits within the memory. (Reply
Br. 4).
Appellants' contention is not persuasive. First, we conclude the
broadest reasonable interpretation of the claimed "threshold of allowable
errors" does not preclude Hashizume's maximum allowable errors from
depending on the available surplus remedy lines and the locations of the
failed bits. Moreover, Appellants fail to cite a more narrow definition of
"threshold of allowable errors" in the Specification.2 Second, Hashizume's
maximum correctable error capacity ("threshold of allowable errors") in a
device with failed bits at locations and surplus remedy lines at a given time
is a determinable number. (Ans. 18; Hashizume, col. 5, l. 65-col. 6, l. 2).

2 Any special meaning assigned to a term "must be sufficiently clear in the
specification that any departure from common usage would be so understood
by a person of experience in the field of the invention." Multiform
Desiccants Inc. v. Medzam Ltd., 133 F.3d 1473, 1477 (Fed. Cir. 1998); see
also Helmsderfer v. Bobrick Washroom Equip., Inc., 527 F.3d 1379, 1381
(Fed. Cir. 2008) ("A patentee may act as its own lexicographer and assign to
a term a unique definition that is different from its ordinary and customary
meaning; however, a patentee must clearly express that intent in the written
description.").
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We also find the limitation at issue would have been taught or
suggested by Hashizume's background description of a prior art device with
no error correction, as discussed above (see Hashizume, col. 1, ll. 10-16).
Specifically, Hashizume's device without error correction is declared failed
if "the test series when the number of errors detected within the test series
exceeds" zero ("a threshold of allowable errors"). We conclude the plain
language of the claim does not require any error correction, thus the
"threshold of allowable errors" is zero and any error fails the device.
For these reasons, on this record, we are not persuaded of Examiner
error. Accordingly, we sustain the Examiner's rejection of claim 7 and of
claim 8, which falls with claim 7.
CLAIM 25
Regarding claim 25's limitation "the error correction circuitry being
configured to correct a prescribed number of bit errors in the integrated
circuit device" (emphasis added), Appellants contend:
[I]n the arrangement disclosed by Hashizume, it is the physical
arrangement of bit errors, rather than the number of bit errors,
which determines whether a bit error can be corrected using
Hashizume's remedy lines. See, for example, Hashizume at
column 9, lines 11-27, with reference to FIGS. 9-11.
(Reply Br. 5).
Appellants present similar contentions as asserted for claim 7 above.
(Reply Br. 5). For the same reasons stated above with respect to claim 7, we
are not persuaded of Examiner error. First, the claimed "prescribed number
of bit errors" (claim 25) does not preclude the maximum allowable errors
from depending on the available surplus remedy lines and the locations of
the failed bits. Moreover, Appellants fail to cite a more narrow definition of
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"prescribed number of bit errors" in the Specification.3 Second,
Hashizume's maximum correctable error capacity ("error correction circuitry
being configured to correct a prescribed number of bit errors") in a device
with failed bits at locations and a given number surplus remedy lines is a
determinable number. (Ans. 18-19; Hashizume, col. 5, l. 65-col. 6, l. 2).
For these reasons, on this record, we are not persuaded of Examiner
error. Accordingly, we sustain the Examiner's rejection of claim 25.
CLAIMS 28-30
Appellants urge claims 28-30 are patentable for the same reasons we
did not find persuasive regarding the rejection of claim 25. (Reply Br. 5).
Therefore, we sustain the Examiner's rejection of claims 28-30 for the same
reasons discussed above regarding claim 25.

R2.
CLAIM 6
Appellants urge claim 6 is patentable for the same reasons we did not
find persuasive regarding the rejection of claim 1. (Reply Br. 5). Therefore,
we sustain the Examiner's rejection of claim 6 for the same reasons
discussed above regarding claim 1.

DECISION
We affirm the Examiner's rejection R1 of claims 1-5, 7, 8, 10, 12-22,
and 24-30 under § 103.
We affirm the Examiner's rejection R2 of claim 6 under § 103.

3 See n.1 supra.
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No time for taking any action connected with this appeal may be
extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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