Ex Parte Brothers et al

Patent Trial and Appeal Board

Aug 13, 2013

11468435 (P.T.A.B. Aug. 13, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte JOHN BROTHERS, TIMOUR PALTASHEV,
HSILIN HUANG and QUNFENG (FRED) LIAO
____________

Appeal 2010-012045
Application 11/468,435
Technology Center 2600
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Before MAHSHID D. SAADAT, KRISTEN L. DROESCH and
JOHN A. EVANS, Administrative Patent Judges.

DROESCH, Administrative Patent Judge.
DECISION ON APPEAL

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STATEMENT OF THE CASE
The Appellants seek review under 35 U.S.C. § 134(a) of a final
rejection of claims 1-6 and 33-37.1 We have jurisdiction under 35 U.S.C.
§ 6(b). We AFFIRM.
BACKGROUND
The Appellants’ disclosed invention relates to a graphics pipeline
configured to synchronize data processing according to signals and tokens.
The graphics pipeline has at least four components. The first component has
one input and one output and communicates output tokens or wire signals
after receiving tokens on the input, an internal event occurrence, or receipt
of a signal on an input path. The second component has one input and a
plurality of outputs and communicates tokens or wire signals on one of the
outputs after receiving tokens on the input, an internal event occurrence, or
receipt of a signal on an input path. The third component has a plurality of
inputs and one output and communicates tokens or wire signals on the
output after receiving tokens on one of the inputs, an internal event
occurrence, or receipt of a signal on an input path. The fourth component has
a plurality of inputs and a plurality of outputs and has the capabilities of both
the third and fourth components. Abs.; see also Spec. 7-9.
Independent claims 1 and 33 are illustrative and are reproduced below
(disputed limitations in italics):
1. A method for a graphics pipeline to synchronize data
in the graphics pipeline, comprising the steps of:

1 Claims 7-32 have been cancelled.

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receiving one or more input tokens on a data input at a
graphics pipeline component having one data input and one
data output;
receiving one or more input signals on an input signal
path of the graphics pipeline component;
outputting one or more synchronization tokens on the
data output to one or more other components of the graphics
pipeline, wherein the one or more synchronization tokens are
associated with the one or more input tokens, the one or more
input signals, or an internal event of the graphics pipeline
component; and
outputting one or more synchronization signals on an
output signal path of the graphics pipeline component to one or
more other components of the graphics pipeline, wherein the
one or more synchronization signals correspond to the one or
more input tokens, the one or more input signals, or the internal
event.
33. A graphics pipeline system, comprising:
a processing component having one data input, one data
output, one wire signal input, and one wire signal output, the
processing component configured to receive at least an event
start token and an event end token on the data input and to
output the event start token and the event end token on the data
output, the processing component also being configured to
receive at least one of event start and end signals on the wire
signal input path and to output at least one of the event start and
end signals on the wire signal output path;
the processing component having a synchronization
backpressure input configured to communicate with a next
processing component in the graphics pipeline; and
the processing component having a synchronization
backpressure output configured to communicate with a prior
processing component in the graphics pipeline.
Rejections
Claims 1-4 stand rejected under 35 U.S.C. § 102(a) as being
anticipated by Van Hook (U.S. 6,867,781 B1, Mar. 15, 2005).

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Claim 6 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Van Hook.
Claims 5 and 33-37 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Van Hook and Emberling (U.S. 6,833,831, Dec. 21,
2004).
ISSUES
Did the Examiner err in finding that Van Hook describes “outputting
one or more synchronization signals on an output signal path of the graphics
pipeline component to one or more other components of the graphics
pipeline, wherein the one or more synchronization signals correspond to the
one or more input tokens, the one or more input signals, or the internal
event,” as recited in claim 1?
Did the Examiner err in finding that the combination of Van Hook and
Emberling teaches or suggests “receiving a backpressure synchronization
signal from a next component in the graphics pipeline . . . and outputting a
backpressure synchronization signal to a prior component in the graphics
pipeline,” as recited in dependent claim 5, and similarly recited in
independent claim 33?
ANALYSIS
We have reviewed the Examiner’s rejection in light of the Appellants’
arguments in the Appeal Brief. We highlight and address specific findings
and arguments for emphasis as follows.
Rejections of Claims 1-4 and 6 as Anticipated or Obvious over Van Hook
The Examiner finds that Van Hook describes “outputting one or more
synchronization signals on an output signal path of the graphics pipeline

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component to one or more other components of the graphics pipeline.” Ans.
4 (citing col. 10, ll. 15-23). The Appellants argue that Van Hook does not
describe the aforementioned limitations because Van Hook describes a main
processor which writes to a memory that is separate from the graphics
pipeline. Br. 6 (citing col. 10, ll. 18-23) (emphasis in original). The
Appellants’ arguments are unpersuasive. We agree with the Examiner’s
construction of “components of the graphics pipeline” to include any
component which is involved in the graphics processing. Ans. 15. We
further agree with, and adopt as our own, the Examiner’s finding that Van
Hook’s main memory is a component of the graphics pipeline based on Van
Hook’s description that the main memory 112 is shared between the main
processor 110 and the graphics pipeline 180. Id.; see col. 10, ll. 21-22.
We are also not persuaded by the Appellants’ argument that Van
Hook’s description of the “set draw done” command sending a draw-done
token into a first in first out (FIFO) buffer between the main processor 110
and the graphics and audio processor 114 is not equivalent to the disputed
claim limitations. Br. 7 (citing col. 8, ll. 23-38) (emphasis in original). The
Appellants’ argument is not persuasive since the Examiner does not rely on
this portion of Van Hook to address the disputed claim limitations.
Furthermore, according to the Examiner’s broad construction of
“components of the graphics pipeline,” the FIFO buffer, main processor 110
and graphics and audio processor are components of the graphics pipeline.
Also unpersuasive is the Appellants’ assertion that Van Hook does not
describe “wherein the one or more synchronization signals correspond to the
one or more input tokens, the one or more input signals, or the internal

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event” because “it is not clear how the synchronization mechanism relating
to the main processor (allegedly the ‘one or more synchronization signals’)
correspond to either the SetDrawnSync command or the graphics commands
received by the pixel engine.” Br. 7 (emphasis omitted). The Appellants do
not meaningfully explain the error in the Examiner’s findings. We agree
with, and adopt as our own, the Examiner’s finding that Van Hook describes
an interrupt line which is also an output synchronization signal and which is
associated with the token register, which means that the interrupt (i.e., output
synchronization signal) corresponds to the input token. Ans. 15-16 (citing
Van Hook col. 9, ll. 9-23, 45-59); see also Fig. 4 depicting interrupt line 706
and token register 704.
For these reasons, we sustain the Examiner’s rejection of claims 1-4
as anticipated by Van Hook. The Appellants do not separately and
substantively argue the limitations of dependent claim 6. Br. 8. Accordingly,
for the same reasons as claims 1-4, we sustain the rejection of claim 6 as
obvious over Van Hook.
Rejection of Claim 5 as Obvious over Van Hook and Emberling
Claim 5 depends from claim 1 and further recites: “receiving a
backpressure synchronization signal from a next component in the graphics
pipeline; implementing a predetermined action in response to receipt of the
backpressure synchronization signal; and outputting a backpressure
synchronization signal to a prior component in the graphics pipeline in
response to a predetermined event.” The Appellants argue that the secondary
reference Emberling does not: 1) explicitly teach that pixel transfer MUX
206 conveys a suspension instruction (allegedly the “backpressure

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synchronization”) to rasterization pipeline 200; and 2); “in Figs. 8A-8D, no
signals are shown from MUX 206 to rasterization pipeline 200.” Br. 9. The
Appellants further assert that Emberling’s teaching of “[o]nce the
rasterization pipeline 200 enters the suspend mode, a special sync signal
may be generated within the rasterization pipeline 200, and sent to both the
fragment pipeline 204 and the texture pipeline 202 (step 238),” is not
equivalent to “outputting a backpressure synchronization signal to a prior
component in the graphics pipeline.” Br. 9-10 (citing col. 11, ll. 11-15).
The Appellants’ arguments are misplaced and unpersuasive. In
particular, we note that the Examiner does not rely on Emberling’s
description of a suspension instruction to teach a backpressure
synchronization signal. Instead, the Examiner finds that the signal from pixel
transfer MUX 206, which indicates that pixel transfer MUX 206 is servicing
one of the pipelines, teaches the backpressure synchronization signal. Ans.
17-18. We further agree with, and adopt as our own, the Examiner’s finding
that the signal from pixel transfer MUX 206, which indicates that pixel
transfer MUX 206 is servicing one of the pipelines (i.e., texture pipeline
202, fragment pipeline 204), eventually causes a suspension of the
rasterization pipeline 200 (i.e., the north interface 161 is stalled and a
suspend instruction is conveyed to rasterization pipeline 200). Ans. 17-18;
see col. 11, ll. 5-11. We also agree with the Examiner’s finding that the
claim language does not require the claimed components to be adjacent to
each other and does not require the output signal to be direct. Ans. 18.

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For these reasons in addition to those addressed above for claims 1-4,
we sustain the Examiner’s rejection of dependent claim 5 as obvious over
Van Hook and Emberling.
Rejection of Claims 33-37 as Obvious over Van Hook and Emberling
The Appellants argue that the Examiner erred in treating the terms
“event start token” and “event end token” as merely the names of two
tokens. Br. 10 (citing FOA 3). The Appellants contend that claim 33
explicitly defines two types of tokens, which by their plain and ordinary
meanings refer to event-based tokens - one relating to an event start and
another one relating to an event end. Br. 10-11.
The Appellants’ arguments are unpersuasive and we agree with the
Examiner’s position that “event start token” and “event end token” are the
names of two tokens. More specifically, “event start” and “event end” in the
context of the tokens constitute non-functional descriptive material that
merely describes the information intended to be conveyed by the tokens. The
use of “event start” and “event end” in the context of the tokens is not
functionally related to, nor utilized in, the system recited in claim 33. In
other words, the system is not affected, altered, or changed based on the
“event start” or “event end” information to be conveyed by the tokens; the
system structure is the same regardless of the information to be conveyed by
the tokens. We agree with, and adopt as our own, the Examiner’s finding
that Van Hook teaches or suggests the disputed limitations. Ans. 8, 20-21
(citing col. 10, ll. 1-17).
The Appellants also assert that the Examiner improperly concluded
that it would have been obvious to one of ordinary skill in the art to have a

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single component to output and input such a synchronization signal.
However, the Appellants do not meaningfully explain the error of the
Examiner, but instead conclude that the Examiner only provided conclusory
statements and did not provide some articulated reasoning with rationale
underpinning. Br. 11-12 (quoting KSR Int'l Corp. v. Teleflex Inc., 550 U.S.
398, 418 (2007) (quoting In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006))).
We agree with, and adopt as our own, the Examiner’s sufficiently articulated
reasoning with rationale underpinning. Ans. 7 (“The synchronization signal
from downstream element to upstream element provides a facility to control
the upstream operation with the consideration of status of the down stream
operation.”). Moreover, we further note that claim 33 is not limited to a
single processing component. Rather, “a processing component” means one
or more processing components may be included in the recited “graphics
pipeline system, comprising: a processing component.” See KCJ Corp. v.
Kinetic Concepts, Inc., 223 F.3d 1351, 1356 (Fed. Cir. 2000) (citations
omitted) (“[A]n indefinite article ‘a’ or ‘an’ in patent parlance carries the
meaning of ‘one or more’ in open-ended claims containing the transitional
phrase ‘comprising.’”).
Similar to the arguments addressing dependent claim 5, the Appellants
argue that Emberling does not disclose a processing component having a
synchronization backpressure output configured to communicate with a prior
processing component in the graphics pipeline. For the same reasons
explained above addressing claim 5, we are not persuaded by the
Appellants’ argument that Emberling does not teach that the pixel transfer
MUX 206 conveys the suspend instruction to the rasterization pipeline 200.

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Br. 12. We additionally note that “synchronization backpressure” in the
context of the output and input recited in claim 33 also constitutes non-
functional descriptive material that describes the information intended to be
conveyed by the output configured to communicate with a prior processing
component in the graphics pipeline and the input configured to communicate
with the next processing component in the graphics pipeline. The
synchronization backpressure is not functionally related to, nor utilized in,
the system recited in claim 33. In other words, the system is not affected,
altered, or changed based on the synchronization backpressure to be
conveyed by the input or the output; the structure of the system is the same
regardless of the synchronization backpressure information.
For these reasons, we sustain the Examiner’s rejection of claims 33-37
as obvious over Van Hook and Emberling.
DECISION
We AFFIRM the rejection of claims 1-4 under 35 U.S.C. § 102(a) as
anticipated by Van Hook.
We AFFIRM the rejection of claim 6 under 35 U.S.C. § 103(a) as
being unpatentable over Van Hook.
We AFFIRM the rejection of claims 5 and 33-37 under 35 U.S.C.
§ 103(a) as being unpatentable over Van Hook and Emberling.
TIME PERIOD
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
AFFIRMED

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