Ex Parte Brittain et al

Patent Trial and Appeal Board

Sep 30, 2016

13290702 (P.T.A.B. Sep. 30, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/290,702 11/07/2011 Mark A. Brittain
61043 7590 09/30/2016
IBM CORPORATION (MH)
c/o MITCH HARRIS, ATTORNEY AT LAW, L.L.C.
P.O. BOX 7998
A THENS, GA 30604
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
AUS920110271US1 4421
EXAMINER
TSUI, DANIEL D
ART UNIT PAPER NUMBER
2132
MAILDATE DELIVERY MODE
09/30/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte Mark A. BRITTAIN, JOHN STEVEN DODSON,
BENJIMAN L. GOODMAN, STEPHEN J. POWELL,
ERICE. RETTER, and JEFFREY A. STUECHELI
Appeal2015-004625
Application 13/290,702
Technology Center 2100
Before JAMES R. HUGHES, JOHNNY A. KUMAR, and
NATHAN A. ENGELS, Administrative Patent Judges.
HUGHES, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants seek our review under 35 U.S.C. § 134(a) of the
Examiner's Final Decision rejecting claims 11-28, which constitute all the
claims pending in this application. Final Act. 1. 1 We have jurisdiction
under 35 U.S.C. § 6(b ).
We reverse.
1 We refer to Appellants' Specification ("Spec.") filed Nov. 7, 2011; Appeal
Brief ("App. Br.") filed Oct. 24, 2014; and Reply Brief ("Reply Br.") filed
Mar. 3, 2015. We also refer to the Examiner's Answer ("Ans.") mailed Jan.
14, 2015, and Final Office Action (Final Rejection) ("Final Act.") mailed
May 21, 2014.
Appeal2015-004625
Application 13/290,702
Appellants 'Invention
The invention at issue on appeal concerns memory access queuing
requests for high-latency memory operations, specifically controllers and
systems for managing access to memory devices that evaluate whether a
high latency maintenance operation is being performed. Spec. 1 :7-20; 4: 14--
7 :3; Abstract.
Illustrative Claim
Independent claim 11, reproduced below with the key disputed
limitations emphasized, further illustrates the invention:
11. A memory controller for managing access to one or more
memory devices, comprising:
a bus interface for receiving memory access operations
from a bus;
a memory access queue for queuing multiple ones of the
memory access operations in an order of their receipt;
a re-order queue for queuing other multiple ones of the
memory access operations, and from which the memory access
operations are performed out-of-order;
a memory device interface for issuing accesses to the one
or more memory devices in response to the memory access
operations; and
a control logic for controlling the bus interface, the
memory access queue, the memory device interface and the re-
order queue such that an address specified by a given memory
access operation in the memory access queue is compared to
determine whether a high latency maintenance operation is
being performed in a region of the one or more memory devices
that includes the address, and responsive to determining that no
high latency maintenance operation is being performed in the
region of memory that includes the address, the control logic
transfers the memory access operation to the re-order queue, and
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Appeal2015-004625
Application 13/290,702
responsive to determining that a high latency maintenance
operation is being performed in the region of memory that
includes the address, rejects the transferring of the memory
access operation to the re-order queue, whereby transfer of the
memory access operation will be retried at a subsequent time.
Rejections on Appeal
1. The Examiner rejects claims 11, 17, 18, 20, 26, and 27 under 35
U.S.C. § 103(a) as being unpatentable over Ochiai (US 2009/0327623 Al,
published Dec. 31, 2009) and Raj war et al. (US 2009 /0063 773 A 1, published
Mar. 5, 2009) ("Rajwar").
2. The Examiner rejects claims 12-14 and 21-23 under 35 U.S.C.
§ 103(a) as being unpatentable over Ochiai, Rajwar, and Allison et al. (US
2009/0216959 Al, published Aug. 27, 2009) ("Allison").
3. The Examiner rejects claims 15, 16, 24, and 25 under 35 U.S.C.
§ 103(a) as being unpatentable over Ochiai, Rajwar, and Applicant's
Admitted Prior Art ("AAPA").
4. The Examiner rejects claims 19 and 28 under 35 U.S.C.
§ 103(a) as being unpatentable over Ochiai, Rajwar, and Bailey et al. (US
5,557,769, issued Sept. 17, 1996) ("Bailey").
ISSUE
Based upon our review of the administrative record, Appellants'
contentions, and the Examiner's findings and conclusions, the pivotal issue
before us follows:
Does the Examiner err in concluding that Ochiai and Rajwar, would
have taught or suggested
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Application 13/290,702
[comparing] an address specified by a given memory access
operation in the memory access queue ... to determine whether
a high latency maintenance operation is being performed in a
region of the one or more memory devices that includes the
address, and responsive to determining . . . a high latency
maintenance operation is being performed in the region of
memory that includes the address, reject[ing] the transferring of
the memory access operation to the re-order queue ...
within the meaning of Appellants' claim 11 and the commensurate
limitations of claim 20?
ANALYSIS
The Examiner rejects independent claims 11 and 20 in view of Ochiai
and Rajwar. See Final Act. 2-3; Ans. 2--4. Appellants contend that Ochiai
and Raj war do not teach the disputed features of claim 11. App. Br. 6-9;
Reply Br. 2-8. Specifically, Appellants contend that "Ochiai discloses a
memory controller with a reorder queue, but does not disclose any special
handling while high latency operations are present" (Reply Br. 3) and
"Rajwar only discloses encountering a high-latency memory operation and
does not disclose comparing an address specified by a given memory access
operation to determine whether the operation is being performed in a region
of memory that includes the address" (Reply Br. 4).
We agree with Appellants that Rajwar (and Ochiai in combination
with Rajwar) does not teach the recited comparison. See App. Br. 8-9;
Reply Br. 4--7. Indeed, the Examiner fails to sufficiently map or explain
what features of Raj war the recited comparison reads on. See Final Act. 3;
Ans. 3--4.
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Application 13/290,702
Consequently, we are constrained by the record before us to find that
the Examiner erred in concluding that Ochiai and Rajwar teach the disputed
limitations of Appellants' claim 11. Independent claim 20 includes
limitations of commensurate scope. Dependent claims 17, 18, 26, and 27
depend on claims 11. Accordingly, we reverse the Examiner's obviousness
rejection of claims 11, 17, 18, 20, 26, and 27.
With respect to dependent claims 12-16, 19, 21-25, and 28 rejected as
obvious over Ochiai and Rajwar, as well as Allison, AAP A, and Bailey, we
reverse the Examiner's obviousness rejections for the same reasons set forth
with respect to claim 11 (supra). The Examiner does not suggest, and we do
not find that the additional references cure the deficiencies of Raj war
(discussed supra).
CONCLUSION
Appellants have shown that the Examiner erred in rejecting claims
11-28 under 35 U.S.C. § 103(a).
DECISION
We reverse the Examiner's rejections of claims 11-28.
REVERSED
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