Ex Parte Braga

Patent Trial and Appeal Board

May 11, 2016

12967355 (P.T.A.B. May. 11, 2016)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/967,355 12/14/2010 Jose Antonio Braga 9873-2 1467
20792 7590 05/12/2016
MYERS BIGEL & SIBLEY, P.A.
PO BOX 37428
RALEIGH, NC 27627
EXAMINER
RUTZ, JARED IAN
ART UNIT PAPER NUMBER
2133
MAIL DATE DELIVERY MODE
05/12/2016 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte JOSE ANTONIO BRAGA
____________________

Appeal 2014-006337
Application 12/967,355
Technology Center 2100
____________________

Before CARLA M. KRIVAK, MICHAEL J. STRAUSS, and
AMBER L. HAGY, Administrative Patent Judges.

STRAUSS, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from a rejection of claims
1–13, 15, and 17–21. Claims 14 and 16 are canceled. We have jurisdiction
over the rejected claims under 35 U.S.C. § 6(b).
We affirm.
THE INVENTION
The claims are directed to solid state non-volatile storage drives
having self-erase and self-destruct functionality. Spec., Title. Claim 1,
reproduced below, is illustrative of the claimed subject matter:
1. An internal solid state storage drive for a host computer,
comprising:
a solid state memory cell array that includes a plurality of
non-volatile memory cells;
a first processor that is configured to control write
operations to the solid state memory cell array and read
operations from the solid state memory cell array; and
a second processor that is separate from the first processor,
the second processor configured to block erase substantially all
data blocks of the solid state memory cell array in response to a
user input self-erase command.

REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Guthrie US 2005/0189909 A1 Sep. 1, 2005
Hsu US 2006/0109117 A1 May 25, 2006
Robinson US 2007/0101060 A1 May 3, 2007
Salessi US 2007/0165456 A1 July 19, 2007
McLean US 7,519,763 B2 Apr. 14, 2009
Banga US 2009/0187655 A1 July 23, 2009

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REJECTIONS
The Examiner made the following rejections:
Claims 1–8 and 11 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Salessi, Hsu, and McLean. Final Act. 2–7.
Claim 9 stands rejected under 35 U.S.C. §103(a) as being
unpatentable over Salessi, Hsu, and McLean, and Robinson. Final Act. 7–8.
Claim 10 stands rejected under 35 U.S.C. §103(a) as being
unpatentable over Salessi, Hsu, McLean, and Banga. Final Act. 9–10.
Claims 12, 13, 15, 17, and 18 stand rejected under 35 U.S.C. §103(a)
as being unpatentable over McLean, Guthrie, Salessi, and Hsu. Final Act.
10–14.
Claims 19–21 stand rejected under 35 U.S.C. §103(a) as being
unpatentable over McLean, Hsu, and Salessi. Final Act. 14–17.

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellant’s
arguments the Examiner has erred. We disagree with Appellant’s
conclusions. We adopt as our own (1) the findings and reasons set forth by
the Examiner in the action from which this appeal is taken (Final Act. 2–29)
and (2) the reasons set forth by the Examiner in the Examiner’s Answer in
response to Appellant’s Appeal Brief (Ans. 2–24) and concur with the
conclusions reached by the Examiner.
Appellant’s contentions are unpersuasive of Examiner error because
each is based on a logical fallacy, attorney argument unsupported by
sufficient evidence, and/or erroneous conclusions of law. For example,
certain of Appellant’s arguments focus on issues raised based on the bodily
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incorporation of the structure of a specific prior art embodiment into
structure disclosed by another prior art reference rather than addressing the
combinations of prior art teachings found by the Examiner. Appellant’s
contentions are further based on argument that disclosure of a particular
embodiment is itself a teaching away from modifying that embodiment to
incorporate the teachings of another reference. In each case, the Examiner
has thoroughly and convincingly addressed Appellant’s contentions of error
including setting forth detailed findings and conclusions, which we have
fully reviewed, agree with, and adopt as our own. Although the Examiner’s
Answer is complete and persuasive without supplementation or further
explanation, for illustrative purposes, we highlight the following for
emphasis.
Appellant contends the rejection of independent claim 1 is improper
because:
1. The prior art does not teach or suggest using two different processors
for block erasing the solid-state memory cell array. Appeal. Br. 4–7.
2. One skilled in the art would not have combined the prior art
references as suggested by the Examiner. App. Br. 7–9.
3. Salessi is directed to the complete and immediate destruction of
highly sensitive information, teaching away from Hsu’s lengthier
multistage erasure process which may be interrupted prior to
completion. App. Br. 9–10.
4. Salessi’s disclosure of the inadequacy of simple erasure of data
sufficiently disparages erasure as a memory purge technique as taught
by Hsu to constitute a teaching away from combining the references.
App. Br. 10–11.
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In support of contention 1, Appellant argues:
Salessi does not disclose or suggest providing an independent, self-
powered second processor that is configured to block erase
substantially all of the data blocks in the flash memory thereof.
Instead, the identified “second processor” of Salessi, namely the purge
controller 4, is used to destroy the flash memory chip. Nothing in
Salessi suggests block erasing the flash memory instead of physically
destroying it. Thus, Salessi clearly fails to provide the requisite
teachings.
App. Br. 5. Appellant further argues Hsu discloses using a single processor
and, therefore, also fails to teach or suggest the second processor of claim 1.
App. Br. 5–6. The Examiner responds by finding “Salessi expressly teaches
the inclusion of a second processor, purge controller 4.” Ans. 4. Addressing
Hsu, the Examiner finds Hsu’s disclosure of a dispersed deactivation
management unit (“DMU”) architecture at least suggests a second processor
used to block erase a memory. Ans. 3.
Appellant’s argument is unpersuasive because, inter alia, it fails to
address the Examiner’s findings and, instead, attacks the references
individually. Non-obviousness cannot be established by attacking the
references individually when the rejection is predicated upon a combination
of prior art disclosures. See In re Merck & Co. Inc., 800 F.2d 1091, 1097
(Fed. Cir. 1986). In particular, the Examiner relies on Hsu, not Salessi, for
teaching disabling a circuit by performing a block erase of memory as
required by claim 1.1 Final Act. 3, Ans. 4–5. Similarly, the Examiner relies

1 We note in passing and without reliance in our ultimate decision, under a
broad but reasonable interpretation, Hsu’s circuit-disabling destructive purge
includes and teaches erasing blocks of memory in so far as destroying a
circuit necessarily erases (i.e., removes all traces of) any data stored by the
circuit.
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on Salessi, not Hsu, for teaching the claimed second processor for disabling
a circuit (i.e., performing a destructive purge) separate from normal read and
write operations performed by the first processor.2 Final Act. 3, Ans. 3–4.
The Examiner correctly combines these teachings, modifying Salessi’s
second processor to disable a circuit by specifically performing a block erase
as taught by Hsu, and concludes the resultant combination teaches or
suggests the disputed second processor that is separate from the first
processor, the second processor configured to block erase substantially all
data blocks of the solid state memory cell array. Final Act. 3. Therefore,
Appellant’s contention 1 is unpersuasive of Examiner error.
In support of contention 2, Appellant argues one skilled in the art
would have combined the references by modifying Salessi, not only to
incorporate Hsu’s block erase but, also, Hsu’s single processor. App. Br. 6.
However, contrary to Appellant’s premise, we agree with the Examiner in
finding Hsu’s distributed deactivation management unit (DMU) circuitry at
least suggests a second processor to perform block erase functions rather
than a single processor. Ans. 3–4. Furthermore, we are unpersuaded by
Appellant’s argument that, in combining references, the possibility of
alternative combinations renders the combination posited and applied by the
Examiner improper. In particular, we are not convinced by Attorney

2 Although the Examiner further finds “Hsu does not teach using a single
processor to perform standard read and write operations to the flash memory
and to perform a block erase of the flash memory” (Ans. 3, emphasis
added), this finding is in response to Appellant’s argument and is consistent
with Salessi’s teaching of using a separate processor for performing circuit
disabling functions.
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argument alone,3 that one skilled in the art would have ignored and/or
abandoned Salessi’s teaching of using a second, separate processor in favor
of the single-processor solution argued to be taught by Hsu. Therefore
Appellant’s contention 2 is unpersuasive of Examiner error.
Appellant’s contention 3 is likewise unpersuasive of Examiner error.
Appellant provides insufficient evidence in support of the asserted premise
that Hsu’s multistage erasure process is antithetical to and defeats Salessi’s
argued goal of protecting highly sensitive information from improper access
and disclosure. See App. Br. 9–10. Furthermore, as correctly found by the
Examiner, “Salessi does not criticize, discredit, or otherwise discourage the
use of a multi-stage deactivation process, and Applicant has not pointed to
any portion of Salessi to support such an assertion.” Ans. 10. Likewise we
find unpersuasive Appellant’s contention 4 arguing Salessi’s disclosure of
damaging the memory circuits beyond repair to guarantee the stored data
cannot be retrieved teaches away from Hsu’s block erasure technique. See
Ans. 10–12. To the contrary, as found by the Examiner, “Hsu shows that in
the fourth and final deactivation stage, each macro is to be destroyed to the
degree that the resulting heat can destroy the chip, package, and box to a
degree where any reverse engineering becomes nearly impossible.” Ans. 11.
For the reasons discussed supra, Appellant’s contentions of Examiner
error in the rejection of claim 1 are unpersuasive. Similarly, we find
unpersuasive Appellant’s arguments in connection with the rejection of
claims 3, 5, 7, 8, 12, and 17–19 (App. Br. 11–19) for the reasons set forth by

3 Attorney arguments and conclusory statements that are unsupported by
factual evidence are entitled to little probative value. See In re Geisler,
116 F.3d 1465, 1470 (Fed. Cir. 1997); see also In re De Blauwe, 736 F.2d
699, 705 (Fed. Cir. 1984).
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the Examiner (Ans. 12–24.) Accordingly, we affirm the rejection of claims
1–13, 15 and 17–21 under 35 U.S.C. § 103(a).

DECISION
The Examiner’s decision to reject claims 1–13, 15, and 17–21 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED