Ex Parte Bopardikar et al

Patent Trial and Appeal Board

Aug 29, 2016

13591579 (P.T.A.B. Aug. 29, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/591,579 08/22/2012
24227 7590 08/31/2016
EMC CORPORATION
OFFICE OF THE GENERAL COUNSEL
176 SOUTH STREET
HOPKINTON, MA 01748
FIRST NAMED INVENTOR
Raju C. BOPARDIKAR
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
EMC-02- l l 9CON1 3119
EXAMINER
BANSAL, GURTEJ
ART UNIT PAPER NUMBER
2139
NOTIFICATION DATE DELIVERY MODE
08/31/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
Docketing@emc.com
sandy.kulaga@emc.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte RAJU C. BOPARDIKAR, JACOBY. BAST,
GARY A. CARDONE, DAVIDE. KAUFMAN,
STUART P. MACEACHERN, BRUCE D. MCLEOD,
JAMES M. NOLAN JR., ZDENEK RADOUCH, JACK J. STIFFLER, and
JAMES A. WENTWORTH II
Appeal2015-003679
Application 13/591,579
Technology Center 2100
Before ERIC S. FRAHM, JAMES W. DEJMEK, and
SCOTT E. BAIN, Administrative Patent Judges.
BAIN, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 appeal under 35 U.S.C. § 134(a) from the Examiner's
final rejection of claims 1-21, which constitute all claims pending in the
application. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
1 Appellants identify EMC Corporation as the real party in interest. App.
Br. 3.
Appeal2015-003679
Application 13/591,579
STATEMENT OF THE CASE
The claimed invention relates to data processing systems involving
the transfer, manipulation, storage, and retrieval of large amounts of data.
Spec. i-f 1. Claims 1, 11, and 21 are independent. Claim 1, which is
illustrative of the invention, reads:
1. Apparatus for providing high-performance, scalable data
storage services from a plurality of storage devices to a client in
response to data storage requests, the apparatus comprising:
a plurality of storage interface modules, each of which
stores data directed to logical addresses into physical locations
in each of the storage devices; and
a host interface module that receives data storage
requests and, in response to a storage request including a data
object identifier that identifies a data object to be stored and
based on relative activities of the storage interface modules,
dynamically selects logical addresses to which a data object
identified by that request is stored, so that data storage activity
\vill be dynamically distributed across the plurality of storage
devices.
App. Br. 22 (emphasis added).
THE REJECTIONS ON APPEAL
Claims 1, 5-11, and 15-21 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Berenshteyn (US 6,317,808 Bl, issued Nov. 13, 2001)
and Tomita (US 6,233,648 Bl, issued May 15, 2001). Final Act. 2.
Claims 2--4 and 12-14 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Berenshteyn, Tomita, and Han (US 2002/0013879 Al,
published Jan. 31, 2002). Final Act. 5.
2
Appeal2015-003679
Application 13/591,579
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellants'
arguments presented in this appeal. Any other arguments which Appellants
could have made but did not make in the Briefs are deemed to be waived.
See 37 C.F.R. § 41.37(c)(l)(iv). On this record, we are not persuaded the
Examiner erred. We adopt as our own the findings and reasons set forth in
the rejections from which this appeal is taken and in the Examiner's Answer,
and highlight the following for emphasis.
Claims 1, 11, and 21
Appellants argue independent claims 1, 11, and 21 together as a
group, with claim 1 representative of the group. C.F.R. § 41.37(c)(l)(iv).
Appellants contend the prior art cited by the Examiner fails to teach at least
three different elements of claim 1. We address each argument in tum.
Appellants first argue the Examiner erred in finding Berenshteyn
teaches a "plurality of storage interface modules" as recited by the claim.
App. Br. 9-12; Reply Br. 2. Appellants allege the Examiner relied on
Berenshteyn Figure 1 for this element. Id. Figure 1 is reproduced below.
3
Appeal2015-003679
Application 13/591,579
122
Daia Storage System
100
~
102
User Interface
118
(132
v v v •.• v
124 c c c c
Public Switched
Telephone
Network
(PSTN) 126
Memory
136
Operating System
File Handling System
140
142
Load Allocation Proc "-144
Disk space monitor 148
Voice Mail Application '-160
~180
Routing Unit
- _L
lDis~ [ Disk 1 r3 . • . [Disk J
'=Js4-1 ~4-2 '--184-3 '-"-184-N
VG= Voice Card
FIG.1
Figure 1 of Berenshteyn illustrates a data storage system 100 including a
routing unit 180, used "for routing incoming messages to one of a plurality
of disks" (labeled "184-1 to 184-N" in the figure). Berenshteyn, col. 4,
11. 20-23. Figure 1 further includes bi-directional arrows between the
routing unit 180 and each of the plurality of disks.
Appellants contend the Examiner relies on the bi-directional arrows as
constituting the "plurality of storage interface modules" of claim 1. App.
Br. 12. Appellants argue this finding is not supported by the record because
the arrows include "no descriptive text" and Berenshteyn provides "no guide
about any possible functionality [of the arrows]." Reply Br. 2. This
argument, however, is misdirected. The Examiner did not rely solely on the
bi-directional arrows as teaching the disputed claim limitation. Ans. 2-3.
4
Appeal2015-003679
Application 13/591,579
Rather, as the Examiner explains in the Answer, Berenshteyn "describes
storing data in one of [the] plurality of disks (col. 4, lines 45-50 and [the
flow chart of] fig. 5)." Ans. 2. An "interface," the Examiner explains, is
defined as a "shared electrical boundary between parts of a computer
system, through which information is conveyed," id., and Appellants do not
contest this definition. The bi-directional arrows in Figure 1 represent such
a boundary, between the routing unit and plurality of disks shown. The
Examiner has not, therefore, ignored the words "storage" and "modules" in
the claim, as Appellents argue, Reply Br. 3, but rather finds the disputed
limitation in the combination of elements shown in Figure 1. Ans. 2-3. We
agree with this finding.
Appellants next argue the prior art does not teach the storage interface
modules "stor[ing] data directed to logical addresses into the physical
locations in each of the storage devices," as claim 1 requires. App. Br. 14;
Reply Br. 4. The Examiner finds this element in the combination of
Berenshteyn, see supra, and Tomita. Ans. 3. On the record before us, we
discern no error in this finding. Tomita teaches "converting a logical
address into a physical address for accessing the disk." Tomita col. 4, 11. 66-
67; Ans. 3. The flow chart of Tomita Figure 4A confirms storage, on a disk,
of data that had been directed to a logical address. See Fig. 4A ("store block
of write data having logical block address LA in ... write buffer"); Ans. 3.
Appellants' arguments (Reply Br. 3--4) regarding the alleged deficiencies of
Berenshteyn, therefore, do not persuade us of error. See In re Keller, 642
F.2d 413, 426 (CCPA 1981) ("one cannot show non-obviousness by
5
Appeal2015-003679
Application 13/591,579
attacking references individually where ... the rejections are based on
combinations of references"). 2
Finally, Appellants argue the Examiner erred in finding the prior art
teaches selecting logical addresses "in response to a storage request
including a data object identifier that identifies a data object to be stored," as
the claims recite. App. Br. 12-13; Reply Br. 5. Appellants contend neither
reference mentions a "data object identifier." Reply Br. 5---6. The Examiner
responds that while the prior art lacks any element labeled "data object
identifier," the combination of Berenshteyn and Tomita teaches the disputed
limitation. Ans. 4---6. We agree with the Examiner. Obviousness, like
anticipation, is "not an ipsissimis verbis test." In re Bond, 910 F.2d 831, 832
(Fed. Cir. 1990) (citations omitted). As the Examiner explains, Berenshteyn
teaches storing data dynamically across a plurality of storage devices in
"response to relative activities of the storage interface modules." Ans. 5.
Tomita, in tum, teaches the claimed "data object identifier" in what it labels
"logical addresses" (Tomita Figure 4A), which identify the data to be stored.
Ans. 6. The data object identifier in Tomita (labeled "logical address") is
then converted into the "logical address" of claim 1 (labelled "logical block
address" in Tomita) for storing the data. Id. (citing Tomita, col. 5, 11. 52-
60). The Examiner, therefore, did not err in finding the combination of
2 Moreover, as the Examiner explains, Berenshteyn also "strongly suggests
the use of logical addresses" in storing data. Ans. 3 (citing Berenshteyn' s
teaching of "virtual disks" corresponding to physical disks, Berenshteyn,
col. 8, 11. 25-30). The record, therefore, does not support Appellants'
assertion, Reply Br. at 4, that "Berenshteyn does not consider an 'address,'
as claimed."
6
Appeal2015-003679
Application 13/591,579
references teach selecting logical addresses "in response to a storage request
including a data object identifier that identifies a data object to be stored."
For the foregoing reasons, we sustain the Examiner's rejection of
claims 1, 11, and 21under35 U.S.C. § 103(a) as unpatentable over
Berenshteyn and Tomita.
Claims 5 and 15
Appellants argue the Examiner erred in finding Tomita teaches
"identifying a storage location of each stored data object" as required by
claims 5 and 15. App. Br. 15-16. Specifically, Appellants assert Tomita
merely teaches storing "pending write information." Id. at 16. The record
before us, however, does not support this assertion.
Tomita states, "[t]he buffer management data 7 is table data for
managing the logical addresses of the write data held in the write buffer 6."
Tomita col. 5, 11. 7-9 (emphasis added). Thus, as the Examiner finds, the
buffer table of Tomita identifies the "storage location" (location within the
write buffer) of stored data objects (the logical addresses of Tomita).
Ans. 6. Appellants' reply (Reply Br. 8) implies Tomita lacks a "data
object," but we have rejected this argument for the reasons stated above. See
supra.
Accordingly, we sustain the Examiner's rejection of claims 5 and 15
under 35 U.S.C. § 103(a) as unpatentable over Berenshteyn and Tomita.
Claims 6 and 16
Appellants argue the Examiner erred in finding Tomita teaches a
"metadata module" having a metadata memory containing logical addresses
identifying storage locations of the stored data objects, as recited in claims 6
and 16. App. Br. 16. The Examiner finds this element in Tomita's teaching
7
Appeal2015-003679
Application 13/591,579
of a "conversion map" that converts logical addresses into the physical
addresses for accessing the data on the disks. Ans. 6 (citing Tomita col. 4,
11. 65---67).
In contesting the Examiner's finding, Appellants merely quote the
relied-upon passage in Tomita, quote the disputed claim limitation, and
assert "conversion of a logical address into a physical address does not teach
or disclose identifying a storage location of each stored data object." App.
Br. 17 (quotations omitted). As the Examiner finds, however, a physical
address does indeed identify a storage location. See supra; see also Ans. 6.
Appellants' cursory argument does identify any error. See 37 C.F.R.
§ 41.37(c)(l)(iv) (appellants' arguments "shall explain why the examiner
erred as to each ground of rejection contested by appellant[s]").
We, therefore, sustain the Examiner's rejection of claims 6 and 16
under 35 U.S.C. § 103(a) as unpatentable over Berenshteyn and Tomita.
Claims 2 and 12
Appellants argue the Examiner erred in finding Han teaches logical
addresses which "identify unused space" in the plurality of storage devices,
as recited in claims 2 and 12. App. Br. 18-19. The Examiner finds this
element in paragraph 32 of Han, which states, "the lookup table maintains
the logical address that corresponds to the physical address for a sector and
indicates the validity of data stored in the sector." Final Act. 5; Ans. 7. We
are not persuaded the Examiner erred.
Appellants admit, App. Br. 19, that Han teaches the "need[] to look
for a 'vacant or unused sector."' Han further teaches, as the Examiner finds,
the "corresponding logical and physical addresses have a validity identifier
to indicate whether the address has been previously allocated or not."
8
Appeal2015-003679
Application 13/591,579
Ans. 7. Appellants do not explain how Han's identification of unused
logical addresses (unused space), combined with the admitted "need to look
for" this unused space, differs from the preallocation logical addresses
"which identify unused space" recited in the claims.
Accordingly, we sustain the Examiner's rejection of claims 2 and 12
under 35 U.S.C. § 103(a) as unpatentable over Berenshteyn, Tomita, and
Han.
Remaining Claims
Appellant does not argue any of the remaining claims, all of which are
dependent, separately from their base claims discussed above. Accordingly,
we sustain the rejections of remaining claims 3, 4, 7-10, 13, 14, and 17-20
for the same reasons we have sustained the rejections of their base claims.
DECISION
The Examiner's rejections of claims 1-21 are AFFIRMED.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l). See 37 C.F.R.
§ 1.136(a)(l)(iv) (2014).
AFFIRMED
9