Ex Parte Bolken

Board of Patent Appeals and Interferences

Oct 17, 2007

10456455 (B.P.A.I. Oct. 17, 2007)

The opinion in support of the decision being entered today is not binding
precedent of the Board.

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte TODD O. BOLKEN
____________

Appeal 2007-0828
Application 10/456,455
Technology Center 2800
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Decided: October 17, 2007
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Before LANCE LEONARD BARRY, HOWARD B. BLANKENSHIP, and
ALLEN R. MACDONALD, Administrative Patent Judges.

BLANKENSHIP, Administrative Patent Judge.

DECISION ON APPEAL
This appeal involves claims 1 and 4 through 21. We have jurisdiction
under 35 U.S.C. §§ 6(b), 134(a).
Appeal 2007-0828
Application 10/456,455

INTRODUCTION
The claims are directed to an interposer for use in a semiconductor
assembly. An interposer is used for attachment of a semiconductor die to a
carrier substrate. (See Specification ¶ 2.) Claim 1 is illustrative:
1. An interposer for use in a semiconductor assembly,
comprising:

an upper surface:

a perimeter wall substantially encircling the upper surface to
form a recess, the recess having at least a first set of alternate upper
electrical contact pads located therein, the at least a first set of
alternate upper electrical contact pads comprising at least a first upper
electrical contact pad and at least a second upper electrical contact
pad; and

a lower surface having at least a first lower electrical
connection pad located thereon, the at least a first lower electrical
connection pad electrically connected to the at least a first upper
electrical contact pad and the at least a second upper electrical contact
pad.

The Examiner relies on the following prior art references to show
unpatentability:
Lin (Lin ′203) US 5,436,203 Jul. 25, 1995

Lin (Lin ′999) US 5,468,999 Nov. 21, 1995
The rejection as presented by the Examiner is as follows:
1. Claims 1 and 4-18 are rejected under 35 U.S.C § 103(a) as
unpatentable over Lin ′999 and Lin ′203.
Claims 19-21 are objected to as being dependent upon a rejected base
claim, but allowable if rewritten in independent form.
Claims 2 and 3 have been canceled.
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OPINION
The Standing Rejection
Claim 1 is the sole independent claim in this application. The
Examiner offers the teachings of Lin ′999 and Lin ′203 to show prima facie
unpatentability of the claim. The § 103 rejection contends (Answer 3-4) that
Lin ′999 shows all that is required by instant claim 1, except for the
perimeter wall “substantially encircling” an upper surface of the interposer
to form a recess. The rejection turns to Lin ′203 for the perimeter wall
teaching deemed to be missing from Lin ′999.
At the outset, we note that Lin ′203 can be considered merely
cumulative in its teachings with respect to the rejection of claim 1. Lin ′999
describes a semiconductor device 41 (Fig. 3) comprising a semiconductor
die 42 mounted to a package substrate 50. A first recess 56 is formed to
create first bonding tier 52, while a second recess 58 is formed to create a
second bonding tier 54. Semiconductor die 42 is mounted within recess 56
and is attached to the substrate by die attach material 36. Lin ′999, col. 5, l.
61 – col. 6, l. 31. The reference depicts, in Figure 3, dam (perimeter wall)
66 as being on only one-half of the device; i.e., the left half as shown in the
drawing. The perimeter wall is not shown as “substantially encircling” the
upper surface of the interposer, however, for the simple reason that the wall
for constraining the flow of liquid encapsulant upon dispensing or reflow is
optional. Lin ′999, col. 6, l. 59 – col. 7, l. 4. Thus, while Lin ′999 describes
an embodiment in which there is no perimeter wall in place, the reference
describes another embodiment where a perimeter wall “substantially
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Application 10/456,455

encircles” the upper surface of the interposer to form a recess, as recited by
instant claim 1.
In any event, Appellants do not contest the finding that the references
teach a “perimeter wall” as claimed. Appellants argue, however, that the
references do not teach the claimed electrical contact pads, which the
Examiner contends is met by Lin ′999.
The Examiner reads the (claim 1) first set of alternate electrical
contact pads on bond posts 20 (Lin ′999 Fig. 3) and the first lower electrical
connection pad on conductive terminal pad 32. The Examiner finds that
these pads are “electrically connected,” as claimed, because electrical
current passes through bumps 34 and vias/traces 22, 18 to pads 20. Pads 20
are, in turn, electrically connected to die pads on chip 42 via bonding wires
60, 62. (Answer 3.)
Appellant submits that such an electrical connection would require
that bond pads 20 of Lin ′999 be “electrically connected” to one another
through the semiconductor die 42. In Appellant’s view, the semiconductor
die would cease to be an operable device when electrical shorts are provided
between the bond pads 20 through the semiconductor die 42. (Reply Br. 5.)
As known in the art, a semiconductor die typically
includes relatively many bond pads configured to carry
signal voltages to individual components of the
integrated circuit contained within the die, a relatively
few bond pads configured for supplying a power voltage
to the die, and a relatively few bond pads configured for
supplying a ground voltage to the die. Appellant admits
that it may be feasible to electrically connect different
power bond pads 20 through the semiconductor die 42,
or different ground bond pads 20 through the
semiconductor die 42 without destroying or precluding
operation of the device. Lin 999 does not, however,
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Application 10/456,455

teach or suggest that any of the bond pads 20 disposed on
the upper surface of the semiconductor die 42 are
electrically connected to one another through the die 42.
Moreover, Lin 999 and Lin 203, when combined, make
no such teaching or suggestion.

(Reply Br. 5-6.)

Appellant seems to acknowledge the unpatentability of the invention
set forth by instant claim 1. If, for example, the two labeled bond pads 20
shown in Figure 3 of Lin ′999, and a terminal pad 32 connected to one of the
two bond pads 20, are at ground potential, then the bond pads 20 are
“electrically connected” by the ground plane within semiconductor die 42.
If the three pads all supply power voltage, then the two labeled bond pads 20
are also “electrically connected” by internal (shorting) connections within
semiconductor die 42. The artisan would recognize that the terms of claim
1, even using Appellant’s unduly narrow meaning of “electrically
connected,” would be met in a normal course of supplying ground and a
power voltage to the die 42. Claim 1 does not require that all pads be
“electrically connected,” but requires only that a minimum of three pads be
so connected. “What matters is the objective reach of the claim. If the claim
extends to what is obvious, it is invalid under § 103.” KSR Int’l Co. v.
Teleflex Inc., 127 S. Ct. 1727, 1742, 82 USPQ2d 1385, 1397 (2007)).
Moreover, Appellant does not point to any definition from the
Specification, nor provide any extrinsic evidence of the artisan’s
understanding, to indicate that “electrically connected” is limited to
electrical shorts between components; i.e., connection by means of
conductive paths without any other intervening elements between the
components. Even if the bond pads 20 depicted in Figure 3 of Lin ′999 were
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at different potentials and provided for different purposes (e.g., ground and
power supply), the pads are electrically connected through semiconductor
die 42 even if there are electrical elements within the die that separate the
bond pads. A power supply voltage and a ground potential within the same
semiconductor chip are electrically connected, at least for the reason that
conventional electrical current flows from the power supply source to the
ground plane.
What a reference teaches is a question of fact. In re Baird, 16 F.3d
380, 382, 29 USPQ2d 1550, 1552 (Fed. Cir. 1994); In re Beattie, 974 F.2d
1309, 1311, 24 USPQ2d 1040, 1041 (Fed. Cir. 1992). We are not persuaded
that the Examiner’s findings with respect to Lin ′999 are erroneous.
Appellant provides a heading in the Brief (at 13) that suggests there is
no reasonable expectation of success in combining Lin ′999 and Lin ′203.
First, as we have noted, the teachings of Lin ′203 can be considered merely
cumulative in the rejection of instant claim 1; a combination of references is
not required. The remarks under the heading are based, however, on the
position that some modification of the electrical contact pads of Lin ′999 is
necessary to demonstrate a prima facie case of obviousness. Appellant has
not shown any modification to be necessary, because Appellant has not
shown error in the Examiner’s findings with respect to Lin ′999.
We have considered all of Appellant’s arguments in support of
claim 1. We sustain the rejection of the claim. Depending claims 4 through
18, not separately argued, fall with claim 1. See 37 C.F.R. §
41.37(c)(1)(vii).

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New Ground of Rejection
In the Examiner’s non-final rejection mailed November 16, 2004, the
Examiner objected to claims 19 through 21 as containing allowable subject
matter. We consider the Examiner’s apparent interpretation of the claims to
be unduly narrow, and enter a new ground of rejection against claims 19
through 21.
Claims 19-21 are hereby rejected under 35 U.S.C § 103(a) as
unpatentable over Lin ′999 and Lin ′203. The claims depend from
independent claim 1. We adopt the Examiner’s findings as set out in the
Answer as they relate to base claim 1.
Claim 19 recites that the perimeter wall of claim 1 is positioned to
create a flow space between itself and at least a portion of an edge of a
semiconductor die when the semiconductor die is positioned in the recess,
such that an underfill encapsulant may be flowed between the upper surface
(that the perimeter wall substantially encircles) and the semiconductor die
therethrough. The perimeter wall or dam 66 of Lin ′999 (col. 6, l. 66 –
col. 7, l. 4; Fig. 3) is positioned as recited in the claim. The positioning of
the perimeter wall in Lin ′999 does not, to any extent, prevent an underfill
encapsulant being flowed between the upper surface and the semiconductor
die therethrough.
Lin ′999 describes a die attach material 36 to mount the die to package
substrate 50 (col. 5, ll. 4-8), with wire bonds 60, 62 (Fig. 3) for electrical
connections to the chip (col. 6, ll. 32-58). Lin ′999 teaches that a liquid
encapsulant 40 may be used to avoid touching of the wire bonds during
encapsulation, and that a dam 66 may be included to constrain the flow of
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Application 10/456,455

the liquid encapsulant during dispensing or reflow (col. 6, l. 59 - col. 7, l. 4).
Lin ′203 describes a dam structure 40 (Fig. 4) to constrain the flow of liquid
encapsulant 38 during dispense (col. 4, l. 58 – col. 5, l. 33). Die 32 is
attached to substrate 12 by an epoxy die attach material 34, with electrical
connections via wire bonds 36. Lin ′203, col. 4, ll. 32-38. Neither reference
depicts an underfill encapsulant in the drawings, such as shown in Figure 4
(reference numeral 102) of the instant disclosure. (See Specification ¶¶ 37-
38.)
Instant claim 19, however, does not require an underfill encapsulant.
The claim is directed to positioning of the perimeter wall.1 Claims 20 and
21 are not directed to an underfill encapsulant, but to a “flow space” created
by the positioning of the perimeter wall. The only thing in the claims to
“configure” the flow space is the positioning of the perimeter wall. As we
have indicated, the positioning of perimeter wall 66 in Lin ′999 does not
prevent the flow of any flowable substance, including that of an underfill
encapsulant.
We thus conclude that, on this record, the further limitations of claims
19 through 21 are met by Lin ′999. We therefore reject the claims under 35
U.S.C. § 103(a) over Lin ′999 and Lin ′203, pursuant to our authority under
37 C.F.R. § 41.50(b).

1 Even if the claim were to be read as requiring an underfill encapsulant, an
underfill encapsulant is conventional for flip chip attachments (Specification
¶¶ 6, 7, 13, 14), which Lin ′203 expressly discloses (col. 4, ll. 38-40) in
combination with dams 40 and 44 (Fig. 4).

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CONCLUSION
The rejection of claims 1 and 4-18 under 35 U.S.C § 103(a) as
unpatentable over Lin ′999 and Lin ′203 is affirmed.
A new rejection of claims 19-21 under 35 U.S.C. § 103(a) over Lin
′999 and Lin ′203 is set forth herein.
With respect to the affirmed rejection(s), 37 C.F.R. § 41.52(a)(1)
provides that “Appellant may file a single request for rehearing within two
months from the date of the original decision of the Board.”
In addition to affirming the Examiner’s rejection(s) of one or more
claims, this decision contains a new ground of rejection pursuant to
37 C.F.R. § 41.50(b). 37 C.F.R. § 41.50(b) provides that “[a] new ground of
rejection pursuant to this paragraph shall not be considered final for judicial
review.”
37 C.F.R. § 41.50(b) also provides that the Appellant, WITHIN TWO
MONTHS FROM THE DATE OF THE DECISION, must exercise one of
the following two options with respect to the new ground of rejection to
avoid termination of the appeal as to the rejected claims:

(1) Reopen prosecution. Submit an appropriate amendment of
the claims so rejected or new evidence relating to the claims so
rejected, or both, and have the matter reconsidered by the
examiner, in which event the proceeding will be remanded to
the examiner. . . .

(2) Request rehearing. Request that the proceeding be reheard
under § 41.52 by the Board upon the same record. . . .

Should the Appellant elect to prosecute further before the Examiner
pursuant to 37 C.F.R. § 41.50(b)(1), in order to preserve the right to seek
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review under 35 U.S.C. §§ 141 or 145 with respect to the affirmed rejection,
the effective date of the affirmance is deferred until conclusion of the
prosecution before the Examiner unless, as a mere incident to the limited
prosecution, the affirmed rejection is overcome.
If the Appellant elects prosecution before the Examiner and this does
not result in allowance of the application, abandonment or a second appeal,
this case should be returned to the Board of Patent Appeals and Interferences
for final action on the affirmed rejection, including any timely request for
rehearing thereof.

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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).

AFFIRMED -- 37 C.F.R. § 41.50(b)

tdl/gw

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