Ex Parte Boldryev et al

Patent Trial and Appeal Board

Aug 19, 2016

13018022 (P.T.A.B. Aug. 19, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/018,022 0113112011
11764 7590
Ditthavong & Steiner, P,C,
44 Canal Center Plaza
Suite 322
Alexandria, VA 22314
08/23/2016
FIRST NAMED INVENTOR
Sergey Boldryev
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
P4976USOO 7799
EXAMINER
HUYNH,KIMT
ART UNIT PAPER NUMBER
2185
NOTIFICATION DATE DELIVERY MODE
08/23/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docket@dcpatent.com
Nokia.IPR@nokia.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SERGEY BOLDYREV,
JARI-WKKA HARALD KAAJA, HANNU ENSIO LAINE,
WKKA HONKOLA, VESA-VEIKKO LUUKKALA, and
IAN JUSTIN OLIVER
Appeal2015-004213
Application 13/018,022
Technology Center 2100
Before NATHAN A. ENGELS, CARLL. SILVERMAN, and
JOYCE CRAIG, Administrative Patent Judges.
ENGELS, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a rejection of claims
1-20. We have jurisdiction under 35 U.S.C. § 6(b ).
We reverse.
Appeal2015-004213
Application 13/018,022
ILLUSTRATIVE CLAIM
Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. A method comprising:
determining energy availability information associated
with at least one level of a computational architecture executing
at least one portion of one computation closure;
determining energy consumption information associated
with the at least one portion of one computation closure; and
processing and/or facilitating a processing of the energy
availability information, the energy consumption information, or
a combination thereof to determine whether to migrate the at
least one portion of one computation closure to at least one other
level of the computational architecture.
THE REJECTIONS
Claims 1--4, 8-14, and 18-20 stand rejected under 35 U.S.C. § 102(b)
as anticipated by Miller et al. (US 2009/0109230 Al; Apr. 30, 2009).
Claims 5-7 and 15-17 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable in view of Miller and DeHaan (US 2011/0055588 Al;
Mar. 3, 2011).
ANALYSIS
The Examiner finds Miller discloses redistribution of computational
processes between different types of processors (such as CPU, GPU, and
DSP) from different subsystem devices, and the different processors in
Miller are equivalent to levels of computational architecture. Ans. 8 (citing
Miller i-fi-12-5, 32-34, 43). Appellants argue the Examiner erred in finding
the different processors types (e.g., CPU, GPU, and DSP) disclosed in Miller
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Appeal2015-004213
Application 13/018,022
constitute different levels of computational architecture as required by claim
1. App. Br. 7.
According to Appellants, subsystems having different processors as
described in Miller would each be associated with just one level of
computational architecture, and Miller therefore does not disclose processing
information "to determine whether to migrate the at least one portion of one
computation closure to at least one other level of the computational
architecture." App. Br. 7. Appellants cite the Specification's statement that
"a computational architecture consists of a plurality of architectural levels,
including a device level, and infrastructure level, and a cloud computing
level" (Spec. i-f36) and argue "to migrate the at least one portion of one
computation closure to at least one other level of the computational
architecture" must be interpreted with the understanding that "the
computational architecture consists of a plurality of architectural levels,
including a device level, and infrastructure level, and a cloud computing
level" (Reply Br. 5).
We are persuaded of error in the Examiner's rejection. While
Appellants' Specification does not provide an explicit definition of the term
"levels of computational architecture," we agree with Appellants that the
plain language of claim 1 viewed in light of Appellants' Specification would
not include Miller's disclosures of different types of processors as a teaching
of levels of computational architecture as claimed. We find nothing in
Appellants' Specification that supports the Examiner's interpretation of
levels of computational architecture as different types of processors. Cf
Spec. i1 3 6 (citing device, infrastructure, and cloud levels as examples of
levels of computational architecture; additionally describing as examples
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Appeal2015-004213
Application 13/018,022
components of infrastructure levels such as backbones, routers, and base
stations that can execute computational closures).
Accordingly, on the record before us, we do not sustain the
Examiner's rejection of independent claims 1 and 11, nor of dependent
claims 2-10 and 12-20, under 35 U.S.C. § 102(b). Because the Examiner's
rejections of claims 5-7 and 15-17 under 35 U.S.C. § 103(a) do not identify
any additional teachings of Miller or any teachings in the other applied prior
art to overcome the deficiencies of Miller, we also do not sustain those
rejections.
DECISION
We reverse the Examiner's rejections of claims 1-20.
REVERSED
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