Ex Parte Black et al

Patent Trial and Appeal Board

Mar 30, 2016

12878542 (P.T.A.B. Mar. 30, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/878,542 09/09/2010
16501 7590
Timothy M, Honeycutt
Attorney at Law
37713 Parkway Oaks Ln.
Magnolia, TX 77355
04/01/2016
FIRST NAMED INVENTOR
Bryan Black
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
AMDI:238\HON 5173
EXAMINER
LI,MEIYA
ART UNIT PAPER NUMBER
2811
NOTIFICATION DATE DELIVERY MODE
04/01/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
timhoney@sprynet.com
timhoneycutt@earthlink.net
elizabethahoneycutt@earthlink.net
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte BRYAN BLACK, MICHAEL Z. SU, GAMAL
REF AI-AHMED, JOE SIEGEL, and SETH PREJEAN
Appeal2014-001446
Application 12/878,542
Technology Center 2800
Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and
JAMES C. HOUSEL, Administrative Patent Judges.
TIMM, Administrative Patent Judge.
DECISION ON APPEAL 1
STATEMENT OF CASE
Appellants2 appeal the Examiner's decision to reject claims 1-14 and
23-25. We have jurisdiction under 35 U.S.C. §§ 6(b) and 134(a).
We REVERSE.
1 In our opinion below, we refer to the Specification filed Sept. 9, 2010
(Spec.), Final Office Action mailed Nov. 5, 2012 (Final), the Appeal Brief
filed May 8, 2013 (Appeal Br.), the Examiner's Answer mailed Aug. 20,
2013 (Ans.), and the Reply Brief filed Oct. 18, 2013 (Reply Br.).
2 Appellants' identify the real party in interest as Advanced Micro Devices,
Inc. Appeal Br. 6.
Appeal2014-001446
Application 12/878,542
The claims are directed to a method of manufacturing a
semiconductor chip having a plurality of conductive vias in a layer of a
semiconductor chip in ohmic contact with a first conductor structure such as
a conductor pad. Spec. i-f 6. Claim 1 is illustrative:
1. A method of manufacturing, comprising:
forming a first plurality of conductive vias in a layer of a
first semiconductor chip, the first plurality of conductive vias
including first ends and second ends;
forming conductive via extensions on each of the first
ends of the first conductive vias; and
forming a first conductor pad in ohmic contact with the
conductive via extensions.
Claims Appendix, Appeal Br. 32.
The Examiner maintains the following rejections:
A. Claim 10 rejected under 35 U.S.C. § 112 i-f 2;
B. Claims 1-3, 5-7, 9, 10, and 12-14 under 35 U.S.C. § 102(e) as
anticipated by Uchiyama; 3
C. Claims 1-14 under 35 U.S.C. § 103(a) as obvious over Cobbley4 in
view of Uchiyama; and
D. Claims 23-25 under 35 U.S.C. § 103(a) as obvious over Uchiyama
in view of Bae. 5
3 Uchiyama, US 2008/0237806 Al; published Oct. 2, 2008.
4 Cobbley et al., US 2009/0294983 Al; published Dec. 3, 2009.
5 Bae et al., US 2009/0261458 Al; published Oct. 22, 2009.
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Appeal2014-001446
Application 12/878,542
Rejection A
ANALYSIS
The Examiner rejects claim 10 as indefinite because "[t]he claimed
limitation of 'a second and opposite side' ... is unclear as to which side
applicant refers." Final i-f 12.
Claim 10, with emphasis on the limitation at issue, reads:
10. A method of manufacturing, comprising:
forming a first plurality of conductive vias in a layer of a
first semiconductor chip, the first plurality of conductive vias
including first ends and second ends, the first semiconductor
chip having a first side and a second and opposite side;
forming conductive via extensions on each of the first
ends of the first conductive vias;
forming a first conductor structure proximate the first
side and in ohmic contact with the conductive via extensions;
and
forming a second conductor proximate the second side
and in ohmic contact \~1ith the second ends of the first plurality
of conductive vias.
Claims Appendix, Appeal Br. 34 (emphasis added).
The second paragraph of 35 U.S.C. § 112 requires the specification
"conclude with one or more claims particularly pointing out and distinctly
claiming the subject matter which the applicant regards as his invention." 35
U.S.C. § 112, i-f 2 (2010). "As the statutory language of 'particular[ity]' and
'distinct[ ness]' indicates, claims are required to be cast in clear-as opposed
to ambiguous, vague, indefinite-terms." In re Packard, 751F.3d1307,
1313 (Fed. Cir. 2014). Exact precision is not required. The test for
determining the question of indefiniteness may be formulated as whether the
claims "set out and circumscribe a particular area with a reasonable degree
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Appeal2014-001446
Application I2/878,542
of precision and particularity." In re Moore, 439 F.2d 1232, 1235 (CCPA
I 97 I). With regard to the reasonableness standard, one must consider the
language in the context of the circumstances. Packard, 75I F.3d at I3I3.
The language "a second and opposite side" merely designates a side
opposite a first side in the first semiconductor chip. There is no question
that a semiconductor chip has a second side opposite a first side; such as
shown in, for instance, Appellants' Figures I, 2, and 6. According to the
Examiner, "the person of ordinary skill would not understand which side(s)
applicant refers to since the semiconductor chip consists of six surface
sides." Ans. 3--4. But in the context of the claim and the invention
disclosed in the Specification, it appears clear that the first and second sides
designated in the claim are the sides shown as the top side and bottom side
of the chip I5, which are to interface with another chip 25 and a circuit
board, respectively. See, e.g., Figs. I-2; Spec. i-f 24.
The Examiner has not established that claim I 0 fails to set out and
circumscribe what is claimed with a reasonable degree of precision and
particularity.
Rejection B
The Examiner also rejects claims I-3, 5-7, 9, IO, and I2-I4 under
35 U.S.C. § I02(e) as anticipated by Uchiyama.
All of the claims require "forming a first plurality of conductive vias
in a layer of a first semiconductor chip." See, e.g., Claims I, I 0, and 25.
The Examiner finds that Uchiyama shows in Figures IA, IB, 5A-5E
and related text a method including a step of forming a first plurality of vias
G5 (left). Final 6. Appellants correctly point out that Figures IA, IB, and
5A-5E fail to show vias G5. Appeal Br. 21. The Examiner clarifies that it
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Appeal2014-001446
Application 12/878,542
Figure IB is an enlarged view of a portion of the laminated semiconductor
chip device shown in cross-section in Figure 1 A
Through-electrode G3 has an internal conductive film 12a that is
shown in Figure 2A. Figure 2A is reproduced below:
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Appeal2014-001446
Application 12/878,542
Figure 2A is a horizontal sectional view taken along line H-H in Figure lB.
The horizontal cross-section shows that the conductive film 12a of
through-electrode G3 is one block of unitary conductive material with
through-holes filled with pillar semiconductors 1 ld that are surrounded by
internal insulating film 13. Uchiyama i-f 5 8.
Appellants illustrate conductive film 12a as follows:
\
·\
\
\ t3:Jhc·~n E~nd
Appellants' Figure is a 3D pictorial view of conductive film 12a based upon
how conductive film 12a is shown in Uchiyama's Figure 2A
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Appeal2014-001446
Application 12/878,542
Appellants' depiction of conductive film 12a as unitary, but with
through-holes is reasonable given Uchiyama's Figures IB and 2A as
informed by Uchiyama's description. Uchiyama i-f 59.
The Examiner responds that "the term 'via' is a hole etched in the
interlayer dielectric which is then filled with metal to provide vertical
connection between stacked up interconnect metal lines," and "[Uchiyama]
clearly shows in Figs. 5A-5D holes 19 etched in the interlayer dielectric 11
which is then filled with metal 12a." Ans. 5---6. But Figures 5A-5D are, like
Figures IA and IB, cross-sectional views: They do not show the extent of
the conductive film 12a. The conductive film 12a is a unitary conductor and
not a plurality of vias as shown in Figure 2A.
On this record, we agree that Appellants have identified a reversible
error in the Examiner's finding of anticipation because the Examiner has not
established that Uchiyama describes, within the meaning of§ 102, a method
with a step of forming a plurality of conductive vias in a layer of a first
semiconductor chip.
Rejections C and D
In the rejection of claims 1-14 as obvious over Cobbley in view of
Uchiyama and the rejection of claims 23-25 as obvious over Uchiyama in
view of Bae, the Examiner again relies upon Uchiyama as teaching a
plurality of conductive vias. For the reasons discussed above, we agree with
Appellants that the Examiner reversibly erred in finding Uchiyama discloses
a plurality of conductive vias.
CONCLUSION
We do not sustain the Examiner's rejections.
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Appeal2014-001446
Application 12/878,542
DECISION
The Examiner's decision is reversed.
REVERSED
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