Ex Parte Bhattacharya et al

Board of Patent Appeals and Interferences

May 3, 2011

10195527 (B.P.A.I. May. 3, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/195,527 07/16/2002 Surya Bhattacharya 1875.0810001 3815
26111 7590 05/04/2011
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005
EXAMINER
NGUYEN, THANH T
ART UNIT PAPER NUMBER
2893
MAIL DATE DELIVERY MODE
05/04/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
_____________

Ex parte SURYA BHATTACHARYA, MING CHEN, GUANG-JYE,
LIMING TSAU, HENRY CHEN, NEAL KISTLER,
YI LIU, and TZU-HSIN HUANG
_____________

Appeal 2009-009071
Application 10/195,527
Technology Center 2800
______________

Before ROBERT E. NAPPI, THOMAS S. HAHN, and ELENI MANTIS
MERCADER, Administrative Patent Judges.

NAPPI, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2009-009071
Application 10/195,527

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This is a decision on appeal under 35 U.S.C. § 134(a) of the rejection
of claims 1 through 10 and 21 through 31.
We affirm.

INVENTION
The invention is directed a semiconductor wafer configured for in-
process testing. See Specification 3-4. Claim 1 is representative of the
invention and reproduced below:
1. A semiconductor wafer configured for in-process testing of integrated
circuitry fabricated thereon, comprising:
at least two die separated by a scribe area, each of said die having at
least one complementary metal oxide silicon (CMOS) static random access
memory (SRAM) array having a SRAM layout embedded therein among
mixed-signal CMOS circuitry, said mixed-signal CMOS circuitry having
devices with large features sizes compared to similar devices of said
embedded SRAM array;
a first process control monitor (PCM) testline having a first PCM
layout corresponding to said mixed-signal CMOS circuitry; and
a second PCM testline having a second PCM layout comprising a
mini-array of SRAM cells that mimics said SRAM layout of said embedded
SRAM arrays, and
wherein said first and second PCM testlines are formed in said scribe
area.

REFERENCE
Sato US 6,532,579 B2 Mar. 11, 2003

Appeal 2009-009071
Application 10/195,527

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REJECTIONS AT ISSUE
The Examiner has rejected claims 1 through 10 and 21 through 31
under 35 U.S.C. § 102(e) as being anticipated by Sato. Answer 3-6.1

ISSUE
Appellants’ contentions, on pages 11 through 18 of the Brief,2 present
us with the issue: did the Examiner err in finding that Sato teaches a second
PCM layout comprising an array of SRAM cells that mimics the SRAM
layout of embedded SRAM arrays?

ANALYSIS
We have reviewed the Examiners’ rejections in light of Appellants’
arguments that the Examiner has erred.
We disagree with Appellants’ conclusion. We adopt as our own
(1) the findings and reasons set forth by the Examiner in the action from
which this appeal is taken and (2) the reasons set forth by the Examiner in
the Examiner’s Answer in response to Appellants’ Appeal Brief. We concur
with the conclusion reached by the Examiner.
Particularly we are not persuaded of error by Appellants’ argument,
on pages 16 and 17 of the Appeal Brief, which asserts that Sato indicates
that the memory cells in the FPLA have a similar configuration to the
SRAM memory cells, and that “similar” is not the same as mimic. While we

1 Throughout this opinion we refer to the Examiner’s Answer mailed on
April 3, 2007.
2 Throughout this opinion we refer to the Appeal Brief dated December 15,
2008 and Reply Brief dated June 4, 2007.
Appeal 2009-009071
Application 10/195,527

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concur with Appellants’ that similar and mimic are not the same, the term
“mimic” refers to the function whereas the term “similar” refers to the
arrangement. Appellants’ Specification in paragraph 37, discusses that
mimicking is directed to allowing the basic parameters such as cell current
to be monitored. Thus, we interpreted the function of mimicking as being
directed to allowing the parameters of the cell to be monitored, e.g., tested.
The nature of the SRAM in the scribe areas of Sato is to provide test circuits.
Col. 18, ll. 20-36. Further, contrary to Appellants’ argument on pages 2 and
3 of the Reply Brief, we do not find that disclosures in column 18, lines 20-
36 state that only amplifiers and decoders are in the scribe areas. Thus, we
concur with the Examiner’s finding that Sato teaches a second PCM layout
comprising an array of SRAM cells that mimics the SRAM layout of
embedded SRAM arrays. Accordingly, we sustain the Examiner’s
anticipation rejection.

CONCLUSION
Appellants have not persuaded us of error in the Examiner’s decision
to reject claims 1 through 10 and 21 through 31.

ORDER
The decision of the Examiner to reject claims 1 through 10 and 21
through 31 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

Appeal 2009-009071
Application 10/195,527

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AFFIRMED

ELD