Ex Parte Bertacco et al

Patent Trial and Appeal Board

Feb 23, 2016

12178257 (P.T.A.B. Feb. 23, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/178,257 07/23/2008
22045 7590 02/25/2016
BROOKS KUSHMAN P,C
1000 TOWN CENTER
TWENTY-SECOND FLOOR
SOUTHFIELD, MI 48075
FIRST NAMED INVENTOR
Valeria Bertacco
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
UOM3510PUSP 5969
EXAMINER
PATEL, JIGAR P
ART UNIT PAPER NUMBER
2114
NOTIFICATION DATE DELIVERY MODE
02/25/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docketing@brookskushman.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte VALERIA BERTACCO,
TODD MICHAEL AUSTIN, and IL YAW AGNER
Appeal2013-010359
Application 12/178,257 1
Technology Center 2100
Before DEBRA K. STEPHENS, KEVIN C. TROCK, and
JESSICA C. KAISER, Administrative Patent Judges.
STEPHENS, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a rejection of claims
1-17. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
1 According to Appellants, the Real Party in Interest is The Regents of the
University of Michigan. App. Br. 1.
Appeal2013-010359
Application 12/178,257
STATEMENT OF THE fNVENTION
The claims are directed to a state matcher to detect the state of a logic
circuit within a clock cycle. Abstract; Spec. 38:7-39:5. Claim 1,
reproduced below, is illustrative of the claimed subject matter:
1. A method for state matching a microprocessor, the method
compnsmg:
within each of a plurality of clock cycles,
sampling a plurality of signal values indicative of at least
one state of the microprocessor,
comparing at least some of the signal values with one or
more signatures of signal values each representing one or more
predefined states of the microprocessor,
determining whether the at least one state of the
microprocessor is in one of the predefined states based on the
comparison, and
providing output indicating that the microprocessor is in
one of the predefined states.
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Fin
Piper
Tran
US 6,378,097 Bl Apr. 23, 2002
US 2004/0044925 Al Mar. 4, 2004
US 2007/0050610 Al Mar. 1, 2007
REJECTIONS2
Claims 1-3 stand rejected under 35 U.S.C § 103(a) as being
unpatentable over Fin and Tran. Final Act. 3--4.
2 The rejection of claims 1-17 under 35 U.S.C. § 112, first paragraph was
withdrawn by the Examiner. Ans. 2-3.
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Application 12/178,257
Claims 4--17 stand rejected under 35 U.S.C § 103(a) as being
unpatentable over Fin, Tran, and Piper. Final Act. 5-9.
ISSUE
Did the Examiner err by finding the combination of Fin and Tran
teaches or suggests performing method steps for state matching a
microprocessor "within each of a plurality of clock cycles," as recited in
claim 1?
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellants'
arguments that the Examiner has erred. We disagree with Appellants'
conclusions. We adopt as our own the findings and reasons set forth by the
Examiner in the Final Action from which the appeal is taken (Final Act. 3-
9) and the reasons set forth in the Examiner's Answer in response to
Appellants' Appeal Brief (Ans. 2--4). We highlight and address specific
findings and arguments for emphasis as follows.
Appellants argue the combination of Fin with Tran would not result in
a system capable of performing steps for state matching a microprocessor
"within each of a plurality of clock cycles," as recited in claim 1 (App. Br. 4;
Reply Br. 2-3). Specifically, Appellants argue "Fin cannot be modified with
Tran to yield the claimed invention" (App. Br. 4) because Fin's process
steps "require[] several clock cycles to operate" and "Tran cannot start and
complete an instruction (or multiple instructions) within a single clock
cycle" so the combination cannot execute Fin's process within one cycle
(Reply Br. 3; App. Br. 4).
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Appeal2013-010359
Application 12/178,257
We are not persuaded. The Examiner finds, and we agree, Fin teaches
a process to state match a microprocessor including the steps of
"evaluat[ing] the results of [a] test by comparing the state of the
microprocessor with an expected state ... then report[ing] the results of the
test to the tester" (Final Act. 3--4 (citing Fin 7:3-54); see also Ans. 3). The
Examiner further finds, and we agree, Tran "explicitly discloses" a
superscalar processor "in which multiple instructions are executed within a
single clock cycle" (Final Act. 4 (citing Tran i-f 42)). We agree with the
Examiner's conclusion that the combination of Fin and Tran results in
performance of Fin's process within one clock cycle (see Ans. 3--4; see also
Final Act. 4).
Appellants' contentions regarding the operation of Fin and Tran-that
the steps in Fin's process each require one cycle (see App. Br. 4; see also
Reply Br. 3) and that Tran requires multiple cycles to complete an
instruction (Reply Br. 2-3}-are not supported by sufficient evidence of
record. Appellants assert "at least one clock cycle would be required" for
each of Fin's steps, citing columns 3 and 4 of Fin (App. Br. 4). However,
those columns do not include any discussion regarding the number of cycles
each of Fin's steps needs (see Fin 3: 1--4:67). Furthermore, Appellants'
argument that Tran's processor requires multiple clock cycles to complete an
instruction (Reply Br. 3) are based on a Table provided by Appellants of a
"Simple Superscalar Pipeline," but that Table is only supported by attorney
argument, without identification of any description or support in Tran or
otherwise in the record (see Reply Br. 2-3, see also App. Br. 4). See In re
Pearson, 494 F.2d 1399, 1405 (CCPA 1974) ("Attorney's argument in a
brief cannot take the place of evidence."). Moreover, Appellants have not
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Application 12/178,257
presented sufficient evidence that Tran's teaching of a superscalar processor
in which "multiple instructions are executed within a single clock cycle"
(Tran i-f 42) instead means "Tran cannot start and complete an instruction (or
multiple instructions) within a single clock cycle" (Reply Br. 3; App. Br. 4).
Since Appellants' arguments regarding the manner in which Fin and Tran
operate are not supported by sufficient evidence of record, we are not
persuaded that the combination of Fin and Tran does not result in executing
multiple instructions per clock cycle.
Appellants additionally argue "the [E]xaminer's reasoning to support
his prima facie case of obviousness [combining Fin and Tran] is circular"
(App. Br. 4).
We are not persuaded. As discussed above, we agree with the
Examiner's finding that Fin teaches method steps for testing a processor and
Tran teaches superscalar processors in which multiple steps can be executed
within a single clock cycle (Final Act. 3--4 (citing Fin 7:3-54); Final Act. 4
(citing Tran i-f 42)). The Examiner combines the references to result in a
system, which completes multiple steps in a single cycle to "increas[ e]
throughput" (Ans. 4). The Examiner has articulated reasoning with a
rational underpinning to support the obviousness conclusion, namely, that
"increased throughput" would have motivated a person of ordinary skill in
the art to perform Fin's steps in a single cycle based on Tran's teachings.
Appellants have not persuaded us an ordinarily skilled artisan would not
have found using Tran's teaching of executing multiple instructions within a
single clock cycle with Fin's comparing, determining, and providing,
obvious.
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Application 12/178,257
Accordingly, we are not persuaded the Examiner erred in rejecting
independent claim 1 and dependent claims 2-3, not separately argued, under
35 U.S.C. § 103(a) as being unpatentable over Fin and Tran.
Independent claims 4, 9, 13, and 14, and dependent claims 5-8, 10-
12, and 15-17 were not separately argued instead relying on arguments
(App. Br. 5). Accordingly, we sustain the rejection of claims 4--17 under 35
U.S.C. § 103(a).
We further note, while independent claims 4, 9, 13, and 14 recite
performing steps "within each of a plurality of clock cycles," or similarly
"within a single clock cycle," the steps occurring within the single clock
cycle recited in claims 4, 9, 13, and 14 are different than the steps recited in
claim 1; therefore, Appellants' arguments directed to features of claim 1 not
recited in claims 4, 9, 13, and 14, are not persuasive of Examiner error.
DECISION
The Examiner's rejection of claims 1-3 under 35 U.S.C § 103(a) as
being unpatentable over Fin and Tran is affirmed.
The Examiner's rejection of claims 4--17 under 35 U.S.C § 103(a) as
being unpatentable over Fin, Tran, and Piper is affirmed. 3
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv) (2009).
AFFIRMED
3 Should there be further prosecution, the Examiner's attention is directed to
35 U.S.C § 112, first paragraph, regarding claims 4 and 14. Claims 4 and 14
include a step of "reconfiguring" a microprocessor within a single clock
cycle. However, the portions of Appellants' Specification disclosing steps
that may occur within a single clock cycle are directed to matching states
within a single clock cycle, rather than reconfiguring a microprocessor
within a single clock cycle. See Spec. 38:9-39:5; see also App. Br. 3.
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