Ex Parte Berretta

Patent Trial and Appeal Board

Jan 31, 2017

12211504 (P.T.A.B. Jan. 31, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/211,504 09/16/2008 Katiuscia Berretta FR920070101US1 8549
87220 7590 01/31/2017
Walder Intellectual Property Law (END)
C/O Walder Intellectual Property Law, P.C.
17304 Preston Road
Suite 200
Dallas, TX 75252
EXAMINER
HUISMAN, DAVID J
ART UNIT PAPER NUMBER
2183
MAIL DATE DELIVERY MODE
01/31/2017 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KATIUSCIA BERRETTA
Appeal 2016-000900
Application 12/211,5041
Technology Center 2100
Before STEPHEN C. SIU, JOHN D. HAMANN, and ALEX S. YAP,
Administrative Patent Judges.
HAMANN, Administrative Patent Judge.
DECISION ON APPEAL
Appellant files this appeal under 35 U.S.C. § 134(a) from the
Examiner’s Final Rejection of claims 1, 2, 4, 6—9, 14, 15, 17, 19-22, and
24—26. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
THE CLAIMED INVENTION
Appellant’s claimed invention relates to management of large
processing workloads, including by “dividing the large processing workload
into tasks, assigning the tasks to multiple processing resources and managing
1 According to Appellant, the real party in interest is International Business
Machines Corporation. App. Br. 2.
Appeal 2016-000900
Application 12/211,504
non-specialized processing resources.” Spec. 12. Claim 1 is illustrative of
the subject matter of the appeal and is reproduced below.
1. A method, in a data processing system, for scheduling
jobs on a pool of hardware processing resources, the method
comprising:
creating, by a processing device, a first availability chain,
the first availability chain including a first plurality of time
intervals indicating availability of a first hardware processing
resource in the data processing system during the first plurality
of time intervals, wherein the first hardware processing
resource is a first processor;
associating, by the processing device, the first availability
chain with the pool of hardware processing resources, wherein
the pool of hardware processing resources is a set of processors;
acquiring, by the processing device, a second resource
availability chain associated with the pool of hardware
processing resources, the second availability chain having a
second plurality of time intervals indicating availability of a
second hardware processing resource in the data processing
system during the second plurality of time intervals, wherein
the second hardware processing resource is a second processor;
merging, by the processing device, the first plurality of
time intervals with the second plurality of time intervals based
on a relative timing of the first and second plurality of time
intervals to create a timing availability chain of the pool of
hardware processing resources;
simulating, by the processing device, an execution of
scheduled batch jobs based on the timing availability chain of
the pool of hardware processing resources; and
modifying, by the processing device, a placement of a
scheduled batch job within a batch job schedule based on
results of simulating the execution of the scheduled batch jobs.
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Appeal 2016-000900
Application 12/211,504
REJECTION ON APPEAL2
The Examiner rejected claims 1, 2, 4, 6—9, 14, 15, 17, 19-22, and 24—
26 under 35 U.S.C. § 103(a) as being unpatentable over the combination of
Bitar et al. (US 6,353,844 Bl; issued Mar. 5, 2002) (hereinafter “Bitar”) and
Haeri (US 7,793,294 B2; issued Sept. 7, 2010).
ANALYSIS
We have reviewed the Examiner’s rejection in light of Appellant’s
contentions that the Examiner erred. In reaching our decision, we consider
all evidence presented and all arguments made by Appellant.
We disagree with Appellant’s arguments, and we incorporate herein
and adopt as our own the findings, conclusions, and reasons set forth by the
Examiner in (1) the January 5, 2015 Final Office Action (“Final Act.” 2—9);
(2) the April 7, 2015 Advisory Action (“Adv. Act.” 2); and (3) the August
26, 2015 Examiner’s Answer (Ans. 2-4). We highlight and address,
however, specific findings and arguments below for emphasis.
(1) Simulatins an execution of scheduled batch jobs
Appellant argues the combination of Bitar and Haeri, and Bitar in
particular, fails to teach or suggest “simulating ... an execution of scheduled
batch jobs based on the timing availability chain of the pool of hardware
processing resources,” as recited in claim 1, and similarly recited in claims
14 and 21. App. Br. 8—10. Specifically, Appellant argues Bitar instead
teaches identifying “an unallocated open processor width and unallocated
memory allocation equal to the requirements of’ a job. App. Br. 8 (citing
2 The Examiner withdrew the § 112 rejection of the claims on appeal. Apr.
7, 2015 Adv. Act. 2.
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Application 12/211,504
Bitar Figs. 5—7). For example, Bitar’s Figure 6 teaches “a job(Y) ha[ving] a
time equal to 3, a width equal to 1 CPU, and a memory usage of 10
megabytes of memory which equates to a space/time interval having a space
width of 1, space memory usage of 10, and a time length of 3.” Id. (citing
Bitar Fig. 6). According to Appellant, Bitar’s Figure 6 then “merely
identifies an unallocated open processor width and unallocated memory
allocation equal to the requirements of job(Y).” Id. (citing Bitar Fig. 6).
Appellant argues these teachings do not simulate the execution of job(Y),
nor does Bitar need to simulate job(Y) to determine whether the job would
fit in unallocated space because Bitar provides the job definition (i.e., time
equal to 3, a width equal to 1 CPU, and a memory usage of 10) allowing
Bitar to determine directly whether resources are available to meet the job’s
requirements. See App. Br. 8—9. Moreover, Appellant asserts Bitar’s
teachings relate to scheduling jobs, rather than to simulating the execution of
scheduled batch jobs (i.e., already scheduled jobs), and once Bitar schedules
a job, it never simulates the execution of that job. App. Br. 9-10; Reply Br.
2—\ (“Bitar specifically describes that once a job is scheduled, that job
remains in that schedule regardless of any new incoming jobs as, if no
rectangular contiguous allocation can be made within the given completion
time, the user is merely presented with an error.”).
The Examiner finds, and we agree, the combination of Bitar and
Haeri, and Bitar in particular, teaches or suggests the disputed limitation.
See Ans. 2-4; Final Act. 5. Specifically, the Examiner finds, and we agree,
Bitar teaches or suggests simulating the execution of scheduled jobs via a
schedule — a schedule is a simulation because it models, without actually
executing, execution times and resource requirements of batch jobs — in
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Application 12/211,504
order to determine if yet another job can fit somewhere within the schedule.
Ans. 2 (citing Bitar Figs. 5—7); Final Act. 5 (same). In other words, if
job(X) and job(Y) are scheduled already, the schedule shows the simulation
(i.e., when, how long, and what resources these jobs will use when actually
executed) of the execution of these scheduled jobs so that a third job, job(Z),
then can be scheduled. Ans. 2—3; Final Act. 5. We agree with the Examiner
that the disputed limitation does not require “that all jobs are scheduled
before simulation occurs.” Ans. 4.
Furthermore, we find Appellant’s argument (Reply Br. 4) that Bitar
teaches, in contrast to Appellant’s invention, “that once a job is scheduled,
that job remains in that schedule regardless of any new incoming jobs”
inapposite to whether Bitar teaches this disputed limitation. We also find
Appellant has not shown good cause as to why any argument that Bitar
teaches simulating execution of scheduled batch jobs based on priority (see
Reply Br. 3—4) could not have been presented earlier. As such, this
argument has not been considered, and is waived. See Ex parte Borden, 93
USPQ2d 1473, 1473—74 (BPAI2010) (informative) (absent a showing of
good cause, the Board is not required to address arguments in Reply Brief
that could have been presented in the principal Appeal Brief).
(2) Modifying placement of a scheduled batch job
Appellant argues the combination of Bitar and Haeri, and Haeri in
particular, fails to teach or suggest “modifying ... a placement of a
scheduled batch job within a batch job schedule based on results of
simulating the execution of the scheduled batch jobs,” as recited in claim 1,
and similarly recited in claims 14 and 21. App. Br. 11—13. Specifically,
Appellant argues Haeri “merely identifies] how the tasks line up in a time
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Application 12/211,504
frame from TO to TF and, if two tasks overlap but a start time of one of the
two tasks can be adjusted within its task time range, then the start time of the
one task is moved.” App. Br. 12. Appellant contends that this teaching “is
not equivalent to simulating an execution of scheduled batch jobs based on
the timing availability chain of the pool of hardware processing resources.”
Id. Appellant further argues “moving the timing of a job is not based on the
resources that are available but rather moving a start time and is only
performed in scheduling an unscheduled task.” Reply Br. 10. As above,
Appellant also argues Haeri has no need to simulate an execution of task A,
B, C, or any subsequently scheduled task. App. Br. 12.
The Examiner finds, and we agree, the combination of Haeri and Bitar
teaches or suggests the disputed limitation. Ans. 4; Final Act. 5—6. As to
Haeri, the Examiner finds, and we agree, it teaches or suggests referring to a
simulation of tasks A, B, and C (i.e., the schedule for these scheduled batch
jobs) when trying to schedule task D. Ans. 4 (citing Haeri Fig. 4). We also
agree with the Examiner that Haeri teaches “[bjased on the simulation of
scheduled tasks A, B, and C, the system realizes that task D cannot be
scheduled as desired[, and tjherefore, the placement of scheduled job B is
modified in order to execute job D earlier.” Id. (citing Haeri Fig. 5); see
also Final Act. 5 (citing Bitar col. 6,11. 46-48), 6 (citing Haeri Figs. 1, 4—5).
Furthermore, in accordance with the above findings, we also agree with the
Examiner Bitar teaches that the simulation of the execution of the scheduled
batch jobs can be based on timing availability of processing resources. See
Final Act. 5—6 (citing Bitar Figs. 5—7, col. 6,11. 46-48, col. 8,11. 5—8).
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Application 12/211,504
CONCLUSION
Based on our above findings, we sustain the Examiner’s § 103
rejection of claims 1, 14, and 21, as well as the remaining claims on appeal,
for which Appellant did not provide separate arguments for patentability.
DECISION
We affirm the Examiner’s decision rejecting claims 1, 2, 4, 6—9, 14,
15, 17, 19—22, and 24—26.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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