11039308 (B.P.A.I. Feb. 23, 2010)

Ex Parte Berke et al

Board of Patent Appeals and InterferencesFeb 23, 2010

11039308 (B.P.A.I. Feb. 23, 2010)

UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Ex parte STUART ALLEN BERKE and MARK SHAW ____________ Appeal 2009-000888 Application 11/039,3081 Technology Center 2100 ____________ Decided: February 23, 2010 ____________ Before LEE E. BARRETT, LANCE LEONARD BARRY, and ST. JOHN COURTENAY III, Administrative Patent Judges. BARRETT, Administrative Patent Judge. DECISION ON APPEAL This is a decision on appeal under 35 U.S.C. Â§ 134(a) from the final rejection of claims 1-23. We have jurisdiction pursuant to 35 U.S.C. Â§ 6(b). We affirm-in-part and enter a new ground of rejection. 1 Filed January 20, 2005, titled "System and Method for a Non-Uniform Crossbar Switch Plane Topology." The real party in interest is Hewlett-Packard Development Company, LP. Appeal 2009-000888 Application 11/039,308 2 STATEMENT OF THE CASE The invention The invention relates to interconnecting a plurality of processor groups residing in a symmetric multiprocessing (SMP) system using a "non- uniform crossbar switch plane multiprocessing (SMP) system." Each of the processor groups is coupled to the other processor groups by a number of routes at most equal to (N-l), where N equals the number of processor groups. Illustrative claim Claim 1 is reproduced below for illustration: 1. A symmetric multiprocessing (SMP) system, comprising: a plurality of processor groups each having plural processors under direction of a single operating system; and a non-uniform crossbar switch plane system comprising a plurality of routes, such that each of the processor groups are communicatively coupled to the other processor groups by a number of routes at most equal to (N-l), where N equals the number of processor groups. The references cited by the Examiner Greene US 5,930,256 Jul. 27, 1999 Van Duyne US 6,721,313 B1 Apr. 13, 2004 Prakash US 6,742,072 B1 May 25, 2004 Mehra US 2004/0004963 A1 Jan. 8, 2004 (filed Nov. 7, 2002) Appeal 2009-000888 Application 11/039,308 3 Dayan US 2004/0268111 A1 Dec. 30, 2004 (filed Jun. 25, 2003) Bresniker US 7,187,674 B2 Mar. 6, 2007 (filed Oct. 30, 2001) The rejection Claims 1-23 stand rejected under 35 U.S.C. Â§ 103(a) as unpatentable over Mehra and Dayan. The reference to Prakash is cited to show that SMP systems may be used within an Infiniband architecture. Ans. 4. The references to Green, Van Duyne, and Bresniker are cited to show that a fabric interconnection system and a crossbar switch system are "analogous." Ans. 5. These references are not considered because the statement of the rejection must expressly contain a mention of all references applied in the rejection. See In re Hoch, 428 F.2d 1341, 1342 n.3 (CCPA 1970); Ex parte Movva, 31 USPQ2d 1027, 1028 n.1 (BPAI 1993). If a reference is important to the rejection, it should be made a part of the statement of the rejection. PRINCIPLES OF LAW "[T]he test [for obviousness] is what the combined teachings of the references would have suggested to those of ordinary skill in the art." In re Keller, 642 F.2d 413, 425 (CCPA 1981). A rejection under 35 U.S.C. Â§ 103(a) is based on the following factual determinations: (1) the scope and content of the prior art; (2) the level of ordinary skill in the art; (3) the differences between the claimed invention and the prior art; and (4) any objective indicia of non-obviousness. See KSR Int'l Co. v. Teleflex Inc., Appeal 2009-000888 Application 11/039,308 4 550 U.S. 398, 399 (2007) (citing Graham v. John Deere Co., 383 U.S. 1, 17-18 (1966)). Whether there is motivation to combine or modify the references is a question of fact drawing on the factors of Graham. See McGinley v. Franklin Sports, Inc., 262 F.3d 1339, 1351-52 (Fed. Cir. 2001). "[H]owever, the analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim, for a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ." KSR, 550 U.S. at 418. FINDINGS OF FACT Mehra Mehra states in the Background of the Invention: [0006] In a traditional approach, ServerNet networks have been designed with two ports, also called colored ports or "X" and "Y" ports, connected to two complete, independent groups of crossbar switches. The interconnection group is complete because every end node interfaces with each group of crossbar switches and each group of switches interfaces with every node. Moreover, the interconnection group is independent because ports of one type are only connected to other ports of the same type. For example, each of the X ports is only connected via an X fabric to other X ports and each of the Y ports in the network are likewise only connected via a Y fabric to other Y ports. Note here that an X fabric is a group of switches that connect all the X ports and only the X ports in the network (similarly for Y ports). In this way, a fabric of one type is designed independently of other fabrics of other types. Appeal 2009-000888 Application 11/039,308 5 Mehra states in the Summary of the Invention: [0011] In an embodiment of the invention, an interconnect network is designed so as to allow nodes having more than two ports to be interconnected. More particularly, in an embodiment of the invention, each node interfaces with more than two fabrics. Also, all fabrics are incomplete in that not every node interfaces with every fabric, and no fabric interfaces with all the nodes, yet every pair of nodes interfaces to at least one common fabric. The present invention uses nodes that appear together in a fabric as a class of nodes that exhibit similar interconnection properties. The present invention allows for scalable, high-performance and reliable interconnection of large numbers of end nodes while satisfying constraints on architecture of end nodes and networking equipment including fabrics that comprise n-port crossbar switches. [0012] In one embodiment of the invention, a multi-fabric interconnection system is disclosed, comprising k interconnection fabrics and n nodes. The k interconnection fabrics each have a vertex cardinality, m. The n nodes each have p ports, wherein p is greater than two, and wherein every pair of nodes from among the n nodes is interconnected through at least one of the k interconnection fabrics. Also, each of the k interconnection fabrics interconnects less than all of the n nodes. [Emphasis added.] Mehra describes that "each fabric provides redundant connectivity to all nodes to allow continued connectivity in spite of failure of part of a network." Â¶ [0016]. Dayan Dayan is directed to remote power control across multiple nodes of a data processing system. "The system includes one or more nodes, each node including a chassis housing a traditional SMP server." Â¶ [0006]. Appeal 2009-000888 Application 11/039,308 6 THE INVENTION It is helpful to get a complete understanding of the invention before addressing the rejection. Symmetric multiprocessing (SMP) systems employ many parallel- operating central processing units (CPUs) which independently perform tasks under the direction of a single operating system. Spec. Â¶ 1.2 Clusters of processors, such as CPUs, are coupled together by router devices to facilitate communication among the CPUs and other components, such as input/output (I/O) devices. Spec. Â¶ 2. This appears to be admitted prior art. We take Official Notice of the uncontroversial fact that there are many known multiprocessor interconnection systems: bus-oriented systems, ring networks, crossbar-connected systems, two- and three-dimensional meshes, and hypercubes. The invention uses crossbar interconnections. A crossbar interconnection network is an array of individually operated contact pairs in which there is one pair for each input-output combination. Like a telephone switchboard, each crosspoint switch provides dynamic connections between (source, destination) pairs. A processor-to- processor interconnection going through only one crossbar point has a "single-hop," which has a lower latency (time delay) as compared to multiple-hops through a plurality of crossbars. Spec. Â¶ 9. Appellants describe that it is more expensive to fabricate large crossbars than smaller crossbars because of the inherent failure rates of more 2 References are to paragraphs of the Specification as filed. Appeal 2009-000888 Application 11/039,308 7 complicated designs. Spec. Â¶ 7. Furthermore, there are practical limitations which limit the practical size of crossbars. Spec. Â¶ 8. Appellants state: When the number of CPUs employed in an SMP exceeds the number of available ports in a crossbar, then a plurality of crossbars must be employed to provide the desired connectivity between CPUs. Accordingly, the single-hop criteria can not be met for all of the CPUs, and multiple-hops over multiple crossbars will be required for at least some of the SMP CPUs. Spec. Â¶ 10. Appellants describe examples and disadvantages of multiple hops with multiple crossbars with respect to Figures 1B and 1C, where the multiple hops are caused by connections between crossbars. Spec. Â¶Â¶ 12-17. It is stated that "[i]f an SMP system employs crossbars having smaller crossbars (fewer ports) and/or employs greater numbers of CPUs, even more crossbars will be employed. Spec. Â¶ 18. An object of Appellants' invention is "to provide single-hop connectivity between the CPUs of an SMP system when multiple crossbars are employed." Spec. Â¶ 19. In the usual situation described by Appellants, multiple crossbars are required because the number of ports in each crossbar are less than the number of processors to be interconnected. A "uniform switch plane SMP system" 402 is shown in Figure 4. Each processor cluster 412 contains four processors, for a total of sixteen processors. Spec. Â¶ 41. Link paths 414 couple the processors of clusters 412 via the 16-port crossbars 416. Id. Each link may contain a plurality of "lanes," which themselves may comprise a plurality of individual connections. Spec. Â¶ 38. For example, a link may use ten lanes per link Appeal 2009-000888 Application 11/039,308 8 where each lane may employ four high-speed pins. Spec. Â¶ 4. However, for simplicity, we just consider link paths. In the uniform switch plane SMP system, there are 16 ports, one for each of the sixteen processors (although this condition is not required for a uniform switch plane). Each link path shown represents four paths, one for each processor. Each processor cluster is coupled to another processor cluster via four routes. Spec. Â¶ 43. If reliability design criteria specify single contingency reliability (two routes required such that upon loss of one route, at least one other route remains), then only two links between any pair of processors are required. Id. Appellants state that "the SMP system 402 does not constitute an admission of prior art by the Applicant." Spec. Â¶ 42. However, the use of a single 16-port crossbar to connect to sixteen processors appears to be a conventional full crossbar interconnection system as shown, for example, in Appellants' Figure 1A, assuming the processors are SMP processors grouped in clusters of four. A single 16-port crossbar interconnection to 16 processors (in four clusters of four processors each, i.e., N=4) is "a non-uniform crossbar switch plane system comprising a plurality of routes, such that each of the processor groups are communicatively coupled to the other processor groups by a number of routes at most equal to (N-l), where N equals the number of processor groups," as recited in claim 1, because the number of routes is one and claim 1 does not require a plurality of crossbars. In the uniform switch plane SMP system of Figure 4, each additional 16-port crossbar adds one route between processor groups. If the problem is that there must be single contingency reliability, then it seems that the Appeal 2009-000888 Application 11/039,308 9 solution that would be readily apparent to one of ordinary skill in the art would be to use a second 16-port crossbars connecting all of the processors. This solution again corresponds to a "non-uniform switch plane SMP system" because the number of routes would be two and would meet the plurality of crossbar limitations of claims 7, 20, and 23. Similarly, if one skilled in the art wanted to ensure that the processors would always be interconnected if two routes failed, it would be readily apparent that the solution would be to add another 16-port crossbar, so the number of routes would be three; thus, there would still be (N-1) routes. It is only when there are as many crossbars as processor clusters, and the crossbars have the same number of ports as processors, that the system is "uniform." The described invention mostly relates to using partial crossbars, where the number of ports in the crossbar is smaller than the number of processors to be interconnected. Smaller crossbars have a lower system cost and size. Spec. Â¶ 7. "Partial crossbar interconnection" was a well known interconnection technique, where a small set of full crossbars are connected to processors but not to each other. See, e.g., Butts et al., U.S. Patent 5,036,473, issued July 30, 1991, discussed in the new ground of rejection infra. Appellants describe that using partial crossbars was known, as in Figures 1B and 1C, where the crossbars are also connected to each other. However, partial crossbar interconnection do not have to have crossbars connected to each other as shown in Butts. The other aspect of the described invention is the redundancy (number of routes between processors). Appeal 2009-000888 Application 11/039,308 10 CLAIMS 1-3 The rejection The Examiner finds that Mehra describes a non-uniform crossbar switch plane system having a plurality of routes, referring to paragraph [0011]], and that each of the nodes is coupled to other processor groups by a number of routes at most equal to (N-1), where each is coupled via only one route. Final Office Action (FOA) 2-3. The Examiner finds that Mehra describes a multi-computer system, but does not describe a symmetric multiprocessing (SMP) system comprising a plurality of processor groups each having plural processors under the direction of a single operating system. FOA 3. The Examiner finds that Dayan describes an SMP system wherein each node contains a plurality of processor groups and concludes that it would have been obvious to implement the SMP nodes of Dayan in the system of Mehra. FOA 3. Issues Based on the arguments, the issues are: Issue 1: Does Mehra teach or suggest "a non-uniform crossbar switch plane system comprising a plurality of routes, such that each of the processor groups are communicatively coupled to the other processor groups by a number of routes at most equal to (N-l), where N equals the number of processor groups," as recited in claim 1? Appeal 2009-000888 Application 11/039,308 11 Issue 2: Would one of ordinary skill in the art have found it obvious that each node in Mehra could be "plural processors under the direction of a single operating system" in view of the teachings of Dayan? Analysis - Issue 1 Appellants argue that Mehra is not directed to "crossbar switches" as this term is known by one of ordinary skill in the art. Br. 9; Reply Br. 2. It is argued that the Detailed Description section of Mehra never uses the term "crossbar." Br. 9. It is argued that the Summary of the Invention uses the term "crossbar switch" a single time in the context of mentioning types of network equipment and Mehra is not directed to "crossbar switches." Id. The background of the invention in Mehra describes connecting nodes having two ports, also called colored ports or "X" and "Y" ports, to two complete, independent groups of crossbar switches. "The interconnection group is complete because every end node interfaces with each group of crossbar switches and each group of switches interfaces with every node." Â¶ [0006]. Mehra describes an "interconnect network is designed so as to allow nodes having more than two ports to be interconnected," Â¶ [0011], and "[t]he present invention allows for scalable, high-performance and reliable interconnection of large numbers of end nodes while satisfying constraints on architecture of end nodes and networking equipment including fabrics that comprise n-port crossbar switches." Â¶ [0011]. Mehra indicates that the invention is an improvement over the prior art and that the network Appeal 2009-000888 Application 11/039,308 12 interconnection uses crossbar switches. Thus, we find that Mehra teaches, or at least suggests, that the interconnections can be crossbar switches. Appellants argue that Mehra does not teach or suggest a "non-uniform" crossbar switch plane because each node in Mehra directly connects to every other node; thus Mehra shows nodes connecting in a uniform manner. Br. 9; Reply Br. 2. Appellants argue that claim 1 recites a specific type of crossbar switch configuration wherein each processor group is coupled to the other processor groups by of number of routes equal to (N-1), where N equals the number of processor groups; thus Mehra shows nodes connecting in a uniform manner. Br. 10; Reply Br. 2-3. Claim 1 broadly recites that each processor group is connected to the other processor groups by a number of routes at most equal to (N-l), where N equals the number of processor groups. This is, by Appellants' definition, a "non-uniform crossbar interconnection." Mehra describes that "every pair of nodes from among the n nodes is interconnected." Â¶ [0012]. Thus, every node is connected by one route, which is less than N. (Mehra also discusses that there can be a redundant interconnection, Â¶ [0016], but this would still satisfy the (N-1) limitation when N is greater than 2.) Claim 1 merely requires that a node is connected to another node via a crossbar switch plane system and does not recite any more specific structure, such as more than one crossbar. Mehra teaches that nodes are coupled via crossbar switches. Appellants' argument that Mehra shows connection in a uniform manner, and therefore does not teach a non-uniform interconnection, seems to misapprehend the claimed invention. A "uniform crossbar connection," Appeal 2009-000888 Application 11/039,308 13 as described by Appellants with respect to Appellants' Figure 4, requires that each one of N processor groups is connected to the other processor groups by N routes. That is, for four processor groups, N=4, a "uniform crossbar connection" would have four routes; i.e., there would be three redundant routes. A "non-uniform" connection is a connection by less than N routes, which is clearly taught by the one route in Mehra. Conclusion - Issue 1 Mehra teaches a crossbar interconnection for a plurality of nodes and because each node is connected to every other node by one route, Mehra teaches "a non-uniform crossbar switch plane system comprising a plurality of routes, such that each of the processor groups are communicatively coupled to the other processor groups by a number of routes at most equal to (N-l), where N equals the number of processor groups," as recited in claim 1. It appears that claim 1 is broad enough to read on the admitted prior art Appellants' Figure 1A if the 16 CPUs are in four SMP clusters because the limitation of "a number of routes at most equal to (N-l), where N equals the number of processor groups" is met when there is only one route from each processor to every other processor. Claim 1 does not require plural crossbars or any specific interconnections. Analysis - Issue 2 Appellants argue that there is no teaching or suggestion to make the combination because the references are directed to completely different Appeal 2009-000888 Application 11/039,308 14 inventions and to solving completely different problems. Br. 15-16; Reply Br. 3-4. It is argued that the Examiner is impermissibly picking and choosing among unrelated elements or teachings because Mehra discusses a node as being a computer or network-attached input/output (I/O) device having two network ports, not a node with plural processor under the direction of a single operating system. Br. 16; Reply Br. 4. Mehra describes the interconnection of a plurality of nodes, but does not state that each node is a processor group containing plural processors under the direction of single operating system. The structure of the processor in each node is not important to the interconnection description. Dayan describes a system having a plurality of nodes, "each node including a chassis housing a traditional SMP server." Â¶ [0006]. Dayan teaches that a node can be a group of plural processors under the direction of a single operating system. One of ordinary skill in the art would have appreciated from Dayan that a node in Mehra could include a group of plural processors. Each port of the node in Mehra could be a separate processor. The fact that Dayan is not directed to the interconnection problem does not mean its teachings of SMP systems are not relevant to the claimed invention. In addition, it does not appear that Appellants contend that they invented "a plurality of processor groups each having plural processors under the direction of a single operating system." Appellants' disclosed invention appears to be the interconnection of a group of ports where the group of ports could be ports of a single processors or ports of a plurality of processors under direction of a single operating system. Appeal 2009-000888 Application 11/039,308 15 Conclusion - Issue 2 One of ordinary skill in the art have found it obvious that each node in Mehra could be a "processor group . . . having plural processors under the direction of a single operating system" in view of the teachings of Dayan. Conclusion Appellants' arguments are not persuasive. The rejection of claims 1-3 is affirmed. CLAIM 4-6 The rejection The Examiner finds that Mehra does not disclose the example of four crossbars and four nodes, each with three ports, but finds that Mehra describes that n nodes can be connected using k fabrics and that the configuration of claim 4 is one of many possible variations of connecting four nodes and four crossbars each with three ports. The Examiner provides drawings showing possible connections in Mehra. Ans. 6-9. Issue 3 Appellants' arguments that Mehra does not teach "crossbar switches" or "non-uniform" crossbar switches or communication through a "crossbar," Br. 10-11, have been addressed in connection with Issue 1, supra. The arguments that Mehra does not teach that the node has plural processors, Br. 15-16 and Reply Br. 3-4, has been addressed in Issue 2, supra. Appeal 2009-000888 Application 11/039,308 16 The remaining issue, as argued, is: Does Mehra teach or suggest the claimed configuration of first, second, third, and fourth "groups of processors" to first, second, third, and fourth "crossbars," as recited in claim 4? Analysis Appellants argue that Mehra does not teach or suggest the configuration of claim 4. Br. 11-12. While we understand the Examiner's position that many possible interconnections are possible, we do not find the specifics taught in Mehra nor do we find sufficient explanation to support an obviousness rejection. Mehra only describes that crossbars can be used, not the size of the crossbars or the interconnections. The Examiner's drawings show one way that the connections of claim 4 can be realized, but there is no persuasive explanation of how Mehra necessarily leads to this result or why such connection would have been obvious. The Examiner might have made an argument on basic design principles. That is, assuming the problem is that there are 16 SMP processors arranged in four clusters of four processors each, and that only 12-port crossbars were available or economical (ignoring input/output pins), and that three routes between each processor were desired in case of failures, it could be argued that the solution in claim 4 would have been apparent to one of ordinary skill in the art. However, this reasoning is not before us. Appeal 2009-000888 Application 11/039,308 17 Because we would like to see a discussion of this obviousness issue, we enter a new ground of rejection infra. Conclusion The rejection of claims 4-6 is reversed. CLAIMS 7-19 The rejection The Examiner rejects independent claim 7 for the reasons stated with respect to claims 1 and 2. Ans. 11. Issue 4 Appellants' arguments that Mehra does not teach "crossbar switches" or "non-uniform" crossbar switches or communication through a "crossbar," Br. 12-13, have been addressed in connection with Issue 1, supra. The arguments that Mehra does not teach that the node has plural processors, Br. 15-16 and Reply Br. 3-4, has been addressed in Issue 2, supra. The remaining issue, as argued, is: Does Mehra teach or suggest three separate elements of (1) crossbars, (2) link paths, and (3) routes? Analysis We found in Issue 1 that Mehra teaches an interconnection system that uses crossbars. Each connection between a node and a crossbar is a "link path." Each interconnection between a node and another node through Appeal 2009-000888 Application 11/039,308 18 a crossbar switch is a "route." That Mehra does not use Appellants' terminology is not important. Mehra describes that each node is connected to every other node and thus is coupled by one route, which is less than N, the total number of nodes, as described in connection with Issue 1. Claim 7 recites a plurality of crossbars. Since Mehra teaches an interconnection system with crossbars, and states that the fabric provides redundant connectivity, this suggest that there is more than one crossbar for each route. In addition, Mehra describes that prior art networks connected ports using two complete, independent groups of crossbar switches (Â¶ [0006]), which indicates that plural crossbars would have been obvious. Conclusion Mehra teaches or suggests interconnection of nodes using crossbar switches. Mehra teaches the three separate elements of (1) crossbars, (2) link paths, and (3) routes. Accordingly, the rejection of claims 7-19 is affirmed. CLAIMS 20-22 The rejection The Examiner finds that Mehra describe redundant connectivity to all nodes at paragraphs [0016] and [0083]. Appeal 2009-000888 Application 11/039,308 19 Analysis Appellants repeat the arguments for previous claims. Appellants' arguments that Mehra does not teach "crossbar switches" or "non-uniform" crossbar switches or communication through a "crossbar," Br. 13-14, have been addressed in connection with Issue 1, supra. Appellants' arguments that Mehra does not teach that the node has plural processors and that there is no motivation to combine the teachings of Dayan, Br. 15-16 and Reply Br. 3-4, have been addressed in Issue 2, supra. Appellants' arguments that Mehra does not teach or suggest three separate elements of (1) crossbars, (2) link paths, and (3) routes, Br. 13, have been addressed in connection with Issue 4, supra. None of these arguments are persuasive of nonobviousness. Comment: Claim 20 recites connections between first and second processor groups using first and second crossbars, for two routes, but then states that "each of the processor groups are coupled to the other processor groups by a number of routes at most equal to (N-l), where N equals the number of processor groups." Since only two processor groups are recited, and the number of routes is two, this limitation might be considered misdescriptive unless it is presumed that there are other unclaimed processor groups. The language should be clarified. Conclusion The rejection of claims 20-22 is affirmed. Appeal 2009-000888 Application 11/039,308 20 CLAIM 23 The rejection The Examiner relies on the rejection of the previous claims. Ans. 13-14. Analysis Appellants' arguments that Mehra does not teach "crossbar switches" or "non-uniform" crossbar switches or communication through a "crossbar," Br. 14-15, have been addressed in connection with Issue 1, supra. Appellants' arguments that Mehra does not teach that the node has plural processors and that there is no motivation to combine the teachings of Dayan, Br. 15-16 and Reply Br. 3-4, has been addressed in Issue 2, supra. Appellants' arguments that Mehra does not teach or suggest three separate elements of (1) crossbars, (2) link paths, and (3) routes, Br. 14, has been addressed in connection with Issue 4, supra. None of these arguments are persuasive of nonobviousness. The comment regarding claim 20 and only two claimed processor groups is applicable here. Conclusion The rejection of claim 23 is affirmed. NEW GROUND OF REJECTION Claim 4 is rejected under 35 U.S.C. Â§ 103(a) as unpatentable over Butts et al., U.S. Patent 5,036,473, issued July 30, 1991, the admitted prior Appeal 2009-000888 Application 11/039,308 21 art (APA), and what would have been obvious to one of ordinary skill in the art addressing the problem of using partial crossbars. Claim 4 reads on Appellants' Figure 3, where there are double redundancy interconnections; i.e., each processor is connected to every other processor in the other clusters by three routes (Spec. Â¶ 43). As noted by Appellants, the number of contingency (backup) routes are a matter of design choice (Spec. Â¶ 43). The APA at page 1 of the Specification states that SMP systems having clusters of CPUs operating in parallel under a single operating system and connected by crossbars were known. That is, the invention relates to the crossbar interconnection arrangement, not the details of the processors that are being interconnected. Butts describes crossbar connection of plurality of logic chips. Butts describes full crossbar interconnects (col. 15, ll. 18-53) and partial crossbar interconnects (col. 15, l. 54 to col. 18, l. 9). It would have been obvious that the logic chip input/output (I/O) pins in Butts could be for any kind of logic: I/O of combinational logic, I/O of a single processor, I/O of a processor in an SMP systems in the APA, etc. Butts shows in Figures 6 and 7 that each partial crossbar is connected only to logic chips and no partial crossbar is connected to another partial crossbar. Appellants' prior art in Figures 1B and 1C shows connecting partial crossbars together, but Butts teaches, if a reference is even necessary, that partial crossbars do not have to be connected to each other. Butts describes that "[t]he number of crossbar chips need not equal the number of logic chips, as it happens in these examples." Col. 16, ll. 25-26. Appeal 2009-000888 Application 11/039,308 22 Now we set up the problem. One of ordinary skill in the SMP art would appreciate that the number of processors in a cluster and the number of clusters to be interconnected are matters of design choice. Accordingly, consistent with Appellants' example in Figures 3 and 5, assume there are four SMP clusters, each having four processors, for a total of sixteen processors to be interconnected. Each processor in each cluster must be interconnected with every other processor in the other clusters at least once if there is no redundancy and more than once if there is redundancy. If full crossbars are used, a full crossbar with sixteen ports is required (plus any additional ports for I/O). Appellants' prior art Figure 1A shows a full (complete) crossbar with sixteen ports that can be used to interconnect sixteen processors. If one wanted to provide a redundant path in case of failure of the crossbar, it would have been readily apparent to one skilled in the art to provide a second full crossbar. Similarly, if one wanted to provide a second redundant path in case of failure of two crossbars, it would have been readily apparent to one skilled in the art to provide a third full crossbar. The described invention describes using partial crossbars, that is, crossbars having a fewer number of ports than there are processors to be interconnected, e.g., 12-port crossbars when there are sixteen processors. Smaller crossbars have a lower system cost and size. Spec. Â¶ 7. Appellants describe that using partial crossbars was known, as in Figures 1B and 1C, where the crossbars are also connected to each other. However, Butts teaches that partial crossbars do not have to have the crossbars connected to each other. Since the size of the crossbars to be used in a design is a matter Appeal 2009-000888 Application 11/039,308 23 of design choice based on many factors such as size, expense, availability, etc., assume that one skilled in the art was faced with the problem faced by Appellants of connecting sixteen processors using 12-port crossbars. Only two 12-port crossbars are needed for single redundancy. That is, a first 12-port crossbar is coupled to first, second, and third groups of processors. A second 12-port crossbar is coupled to first and fourth groups of processors, leaving four unused ports. If one wanted single contingency reliability (at least two routes required, Spec. Â¶ 43), three 12-port crossbars would necessarily be required. If one wanted double contingency reliability (at least three routes required, each route going through a different crossbar, Spec. Â¶ 43), four 12-port crossbars would necessarily be required and the interconnection is recited in claim 4. The number of routes (amount of redundancy) is a matter of design choice. Thus, when one of ordinary skill in the art is presented with the problem of connecting four clusters of processors, each having four processors, using 12-port crossbars, and specifying three routes between each processor, the solution in claim 4 would have been obvious. See KSR, 550 U.S. at 419-20 ("One of the ways in which a patent's subject matter can be proved obvious is by noting that there existed at the time of invention a known problem for which there was an obvious solution encompassed by the patent's claims."). Appeal 2009-000888 Application 11/039,308 24 CONCLUSION The rejection of claims 1-3 and 7-23 under 35 U.S.C. Â§ 103(a) is affirmed. The rejection of claims 4-6 under 35 U.S.C. Â§ 103(a) is reversed. A new ground of rejection is entered as to claim 4. This decision contains new grounds of rejection pursuant to 37 C.F.R. Â§ 41.50(b). 37 C.F.R. Â§ 41.50(b) provides that "[a] new ground of rejection pursuant to this paragraph shall not be considered final for judicial review." 37 C.F.R. Â§ 41.50(b) also provides that the appellant, WITHIN TWO MONTHS FROM THE DATE OF THE DECISION, must exercise one of the following two options with respect to the new ground of rejection to avoid termination of the appeal as to the rejected claims: (1) Reopen prosecution. Submit an appropriate amendment of the claims so rejected or new evidence relating to the claims so rejected, or both, and have the matter reconsidered by the examiner, in which event the proceeding will be remanded to the examiner. . . . (2) Request rehearing. Request that the proceeding be reheard under Â§ 41.52 by the Board upon the same record. . . . Requests for extensions of time are governed by 37 C.F.R. Â§ 1.136(b). See 37 C.F.R. Â§ 41.50(f). AFFIRMED-IN-PART -- 37 C.F.R. Â§ 41.50(b) Appeal 2009-000888 Application 11/039,308 25 pgc/nhl HEWLETT-PACKARD COMPANY Intellectual Property Administration 3404 E. Harmony Road Mail Stop 35 FORT COLLINS, CO 80528 Application/Control No. 11/039,308 Applicant(s)/Patent Under Reexamination Notice of References Cited Examiner Brian Misiurs Art Unit 2100 Page 1 of 1 U.S. PATENT DOCUMENTS * Document Number Country Code-Number-Kind Code Date MM-YYYY Name Classification x A US-5,036,473 07-1991 Butts et al -- -- B US- C US- D US- E US- F US- G US- H US- I US- J US- K US- L US- M US- FOREIGN PATENT DOCUMENTS * Document Number Country Code-Number-Kind Code Date MM-YYYY Country Name Classification N O P Q R S T NON-PATENT DOCUMENTS * Include as applicable: Author, Title Date, Publisher, Edition or Volume, Pertinent Pages) U V W X *A copy of this reference is not being furnished with this Office action. (See MPEP Â§ 707.05(a).) Dates in MM-YYYY format are publication dates. Classifications may be US or foreign. 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