Ex Parte Berke

Board of Patent Appeals and Interferences

Feb 17, 2011

11158419 (B.P.A.I. Feb. 17, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte STUART ALLEN BERKE
____________

Appeal 2009-008598
Application 11/158,419
Technology Center 2100
____________

Before JOHN A. JEFFERY, THU A. DANG, and DEBRA K. STEPHENS,
Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL1
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-11 and 13-25. We have jurisdiction under 35 U.S.C.
§ 6(b). We affirm.

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.
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Application 11/158,419

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STATEMENT OF THE CASE
Appellant’s invention is a symmetric multi-processor (SMP) computer
with interchangeable processor and I/O modules that each include part of a
cache-coherent system memory to reduce latency. See generally Abstract;
Spec. ¶¶ 0016-23; Figs. 3-5. Claim 1 is illustrative with key disputed
limitations emphasized:
1. A symmetric multi-processor ("SMP") computer that comprises:
a circuit board having sockets;
a processor module coupled to one of said sockets; and
an IO module coupled to one of said sockets,
wherein the processor module and the IO module are members of a set
of interchangeable modules, each module in the set having a portion of a
shared, cache-coherent, SMP system memory.

The Examiner relies on the following as evidence of unpatentability:
Huynh US 5,218,514 June 8, 1993
Wright US 5,918,074 June 29, 1999
Hamilton US 2004/0221039 A1 Nov. 4, 2004
Hewlett-Packard Co., Meet the HP 9000 Superdome Servers, 2004
(“NPL1”).2

MRV Comm., Inc., Network 9000: Modular Console Server, Alarm
Management, 2003, available at www.archive.org (“NPL2”).

THE REJECTIONS
1. The Examiner rejected claims 1-7 and 23-25 under 35 U.S.C. § 103(a)
as unpatentable over NPL1, NPL2, and Wright. Ans. 3-13.3

2 We refer to the cited non-patent literature documents as “NPL1” and
“NPL2,” respectively, for consistency with the parties’ nomenclature.
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2. The Examiner rejected claims 8-10 under 35 U.S.C. § 103(a) as
unpatentable over NPL1, NPL2, Wright, and Huynh. Ans. 13-14.
3. The Examiner rejected claims 11, 13-16, and 19 under 35 U.S.C.
§ 103(a) as unpatentable over NPL2 and Wright. Ans. 15-18.
4. The Examiner rejected claim 17 under 35 U.S.C. § 103(a) as
unpatentable over NPL2, Wright, and NPL1. Ans. 18-19.
5. The Examiner rejected claim 18 under 35 U.S.C. § 103(a) as
unpatentable over NPL2, Wright, and Hamilton. Ans. 19-20.
6. The Examiner rejected claims 20-22 under 35 U.S.C. § 103(a) as
unpatentable over Wright, NPL2, and NPL1. Ans. 20-24.

THE OBVIOUSNESS REJECTION OVER NPL1, NPL2, AND WRIGHT
Regarding representative claim 1, the Examiner finds that NPL1
discloses a SMP computer with every recited feature including shared,
cache-coherent SMP system memory. Ans. 4-5, 25. The Examiner,
however, acknowledges that NPL1 does not disclose (1) interchangeable
processor and I/O4 modules, and (2) the I/O modules have part of system
memory, but cites NPL2 and Wright to cure these respective deficiencies in
concluding that the claim would have been obvious. Ans. 5-6, 25-26.
Although Appellant concedes that Wright’s I/O modules have
memory, Appellant nonetheless argues that this memory is not part of

3 Throughout this opinion, we refer to (1) the Appeal Brief filed February
29, 2008; (2) the Examiner’s Answer mailed May 29, 2008; and (3) the
Reply Brief filed July 11, 2008.
4 Although Wright uses the abbreviation “I/O” for input/output—not “IO” as
in the present application (compare Wright, col. 5, l. 65 with Spec. ¶ 0013;
claim 1 et seq.)—we nonetheless use Wright’s abbreviation “I/O” for all
such references for clarity and consistency.
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system memory, let alone part of “shared, cache-coherent, SMP system
memory” as claimed. Br. 11-12; Reply Br. 2.
The issue before us, then, is as follows:

ISSUE
Under § 103, has the Examiner erred in rejecting claim 1 by finding
that NPL1, NPL2, and Wright collectively would have taught or suggested
an I/O module having part of shared, cache-coherent, SMP system memory?

FINDINGS OF FACT (FF)
1. We adopt the Examiner’s undisputed factual findings regarding the
disclosures to NPL1 and NPL2 (Ans. 4-30) as our own.
2. Wright’s networking system minimizes latency caused by (1)
contention for access to shared memory, and (2) forwarding and/or routing
decision time. Wright, Abstract; col. 1, ll. 6-12.
3. Wright’s distributed memory networking system in Figure 6 stores
received packets/cells in the memory on each I/O module as well as the
CPU/Forwarding Engine (FE) memory. Once the data has been received in
the memory accessible by the CPU/FE, it (1) reads the control information to
determine the port for which the data is destined, and (2) writes to each I/O
module to indicate whether it should keep the data. Wright, col. 3, ll. 8-9;
col. 5, l. 62 – col. 6, l. 9; Fig. 6.
4. Although Wright’s distributed memory networking system reduces
memory system cost and complexity relative to other implementations, it
nonetheless requires (1) a more complex and costly “module”
interconnection bus, and (2) memory on every I/O module. Also, every I/O
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module must have enough memory to receive data from every other I/O
module. Wright, col. 6, ll. 11-18; Fig. 6.
5. “The original SMP architecture is characterized by a shared
memory that is uniformly accessible to each processor via one or more
shared buses.” Spec. ¶ 0001.
6. Appellant’s I/O cell board 210 includes a set of SMP memory
modules 416-419 (516 in Figure 5) and agents 406-409 that operate in the
same manner as those on processor cell board 212. The agents each (1)
implement a memory controller function with a directory to maintain cache
coherence, and (2) operate as a multiport switch routing addressed data to
various destinations. Spec. ¶ 0019; Figs. 4-5.
7. SMP memory modules 316-319 on Appellant’s processor cell
board 212 each include one or more memory buses with one or more
memory chip sockets per bus. Spec. ¶ 0017; Fig. 3.
8. Each interchangeable module in Appellant’s system has a portion
of the cache-coherent SMP memory. Appellant notes that with existing chip
technology, architectures that confine the SMP memory to processor boards
have a relatively high I/O latency, but the proposed architecture places part
of the SMP memory on the I/O cell board. Spec. ¶ 0023.

ANALYSIS
Based on the record before us, we find no error in the Examiner’s
obviousness rejection of representative claim 1 which calls for, in pertinent
part, an I/O module having part of shared, cache-coherent, SMP system
memory. As an initial matter, since Appellant does not dispute the
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Examiner’s findings regarding NPL1 and NPL2—findings that we adopt as
our own (FF 1)—we therefore confine our discussion to Wright.
The Examiner found that NPL1 and NPL2 collectively teach every
feature of claim 1 except for including part of system memory on the recited
I/O modules. Ans. 4-6, 25-26. This finding is corroborated, at least in part,
by Appellant’s own disclosure which at least suggests that providing at least
part of cache-coherent, SMP system memory on processor boards (i.e.,
modules) is well known in the art. See FF 8. The crucial question before us,
then, is whether the Examiner erred in concluding that it would have been
obvious to likewise provide this system memory on an I/O module based on
Wright’s teachings combined with the other cited references.
We see no error in the Examiner’s position. The very essence of
Wright’s distributed memory networking system in Figure 6 is to provide
memory on every I/O module to, among other things, reduce memory
system cost and complexity, yet reduce latency. FF 2-4. Notably, not only
does the CPU/FE communicate with the I/O module memories to transfer
data, but the I/O modules themselves exchange data via these memories. FF
3-4. Given the advantages of distributing memory on-board individual I/O
modules in Wright (id.), we see no reason why Wright would not at least
suggest distributing at least part of cache-coherent, SMP system memory to
these modules as the Examiner indicates, particularly since it is already
known in the art to do so for processor modules. See FF 8.
In short, such an enhancement is nothing more than the predictable
use of prior art elements according to their established functions—an
obvious improvement. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417
(2007). And where, as here, if (1) a technique has been used to improve one
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device (i.e., providing at least part of system memory on processor modules
(Ans. 25; FF 8)), and (2) an ordinarily skilled artisan would recognize that it
would improve similar devices (i.e., I/O modules) in the same way, using the
technique is obvious unless its actual application is beyond his or her skill.
KSR, 550 U.S. at 417. On this record, Appellant has provided no persuasive
evidence proving that such an enhancement would have beyond the level of
ordinarily skilled artisans.
We are therefore not persuaded that the Examiner erred in rejecting
representative claim 1, and claims 2-7 and 23-25 not separately argued with
particularity.

THE OTHER OBVIOUSNESS REJECTIONS
We will also sustain the Examiner's other obviousness rejections of
claims 8-11 and 13-22 (Ans. 13-19). Appellant has not particularly pointed
out errors in the Examiner’s reasoning to overcome the Examiner's
obviousness conclusion, but merely reiterates similar arguments made in
connection with claim 1. App. Br. 12-13. We are not persuaded by these
arguments, however, for the reasons previously discussed. The rejection is
therefore sustained.

CONCLUSION
The Examiner did not err in rejecting claims 1-11 and 13-25 under
§ 103.

ORDER
The Examiner’s decision rejecting claims 1-11 and 13-25 is affirmed.
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Application 11/158,419

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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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