Ex Parte Berglas

Patent Trials and Appeals Board

May 31, 2019

13725424 - (D) (P.T.A.B. May. 31, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/725,424 12/21/2012
104840 7590 06/04/2019
Imagination Technologies
c/o Vorys, Sater, Seymour and Pease LLP
1909 K St., NW
Ninth Floor
Washington, DC 20006
FIRST NAMED INVENTOR
Morrie Berglas
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
070852.000160 1001
EXAMINER
RICHER, AARON M
ART UNIT PAPER NUMBER
2618
NOTIFICATION DATE DELIVERY MODE
06/04/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patlaw@vorys.com
vmdeluca@vorys.com
vorys _ docketing@cardinal_ip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MORRIE BERGLAS
Appeal2018-006827
Application 13/725,424
Technology Center 2600
Before ALLEN R. MacDONALD, DAVID M. KOHUT, and
HUNG H. BUI, Administrative Patent Judges.
BUI, Administrative Patent Judge.
DECISION ON APPEAL
Appellant1 seeks our review under 35 U.S.C. § 134(a) of the Examiner's
Final Rejection of claims 5-25, which are all the claims pending in the application.
App. Br. 17-21 (Claims App.). We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM. 2 Because our reasoning relies on new factual findings and
analyses, we designate our affirmance as a new ground of rejection pursuant to 37
C.F.R. § 41.50(b) to preserve Appellant's procedural safeguards. In re Stepan Co.,
660 F.3d 1341, 1346 (Fed. Cir. 2011).
1 According to Appellant, IMAGINATION Technologies Limited is the real party
in interest. App. Br. 2.
2 Our Decision refers to Appellant's Appeal Brief filed December 18, 2017 ("App.
Br."); Reply Brief filed June 19, 2018 ("Reply Br."); Examiner's Answer mailed
April 19, 2018 ("Ans."); Final Office Action mailed May 16, 2017 ("Final Act.");
and original Specification filed December 21, 2012 ("Spec.").
Appeal2018-006827
Application 13/725,424
STATEMENT OF THE CASE
Appellant's invention relates to a 3-dimensional computer graphic system
[shown in Figure 3] that enables texturing and/or blending operations to be
performed on objects being rendered. Spec. 1: 6-8. According to Appellant, the
invention provides a pixel blending buffer on a graphics chip to enable portions of
a frame buffer to be accessed on a polygon by polygon basis and multiple textures
to be accessed simultaneously in a single blending operation. Spec. 3:22-27, 4:6-
16.
Appellant's Figure 3 shows a modified 3-D pixel pipeline in a graphics chip,
as reproduced below.
Y ..... '-"
•. Iterate texture coordinates,
2............... split large potygons or
. combine small pt)tyg9ris
r- --·-- - --i, . . • • i Calculate te:x. coords,
I
' i Texture read
: )
l 4
i vVrite ports
• ! Blend buffer-
• i Read port's}
i J .................. , ...... ...., ................ ......, ..... .;,.;.....,.·~----·~
To frame buffer
(write once)
FIG~ 3
2
Texture cache Frarne
buffer-
Appeal2018-006827
Application 13/725,424
As shown in Appellant's Figure 3, blend buffer 32 with read and write ports
34-36 is arranged between texture read unit 4 and blend operations unit 8 to
obviate the need to perform a "read-modify-write" operation on the frame buffer.
Spec. 514-18.
Claims 5, 13, and 20 are independent. Claim 5 is illustrative of the claimed
subject matter, as reproduced below with the disputed limitation in italics:
5. i\ 3-D graphics system, comprising a graphics chip, the 3~D
graphics system comprising:
a frame buffer;
a blend buffer, provided in a memory distinct from a memory in
vvhich the frame buffer exists, the blend buffer comprising a plurality
of registers, a first write port, a second write port and at least one read
port, wherein registers of the plurality of registers are assignable to
pixels of one or more primitives:
a texture read unit on the graphics chip coupled frJr reading
from a texture memory and coupled to the first write port of the blend
buffer, the texture read unit operable to receive calculated texture
coordinates from a texture coordinate cakulator, the texture
coordinates for pixels of a polygon, and to use the received calculated
texture coordinates in reading texture data for a plurality of textures
from the texture memory and to store the texture data for the plurality
of textures in the blend buffer in respective registers through the first
write port; and
a blending unit on the graphics chip coupled to the second vvrite
port of the blend buffer, and to the at least or1e read port of the blend
buffer, the blending unit operable to perform a plurality of texturing
passes on the polygon, each pass comprising vvalking the polygon, the
walk comprising reading texture data, from a plurality of the registers,
:for each pixel of the polygor1, producing a b1endir1g output, and
storing the blending output in the plurality of registers, through the
second \vrite port of the b1end buffer, and after completing the
plurality of texturing passes, the blending unit is operable to 111/rite the
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Application 13/725,424
pixelsjhm1 the blend bujfer oncefor the p!ura!izy o.lrexturing passes
ro the }l"arne buJfer as a single vvrite-only rransaction on the.frame
btiffer,
App. Br. 17 (Claims App.).
EVIDENCE CONSIDERED
Baker et al. ("Baker") US 2002/0140703 Al Oct. 3, 2002
Drebin et al. ("Drebin") US 7,034,828 Bl Apr. 25, 2006
Vangemert et al. ("Vangemert") US 6,973,561 Bl Dec. 6, 2005
Mang et al. ("Mang") US 7,111,156 Bl Sept. 19, 2006
Van Hook US 7,847,803 Bl Dec. 7, 2010
Koegel US 5,036,456 B 1 July 30, 1991
McCarthy et al. ("McCarthy") us 5,666,509 Sept. 9, 1997
Jarvis US 2003/0014614 Al Jan. 16,2003
Eckart et al. ("Eckart") us 5,574,847 Nov. 12, 1996
EXAMINER'S REJECTIONS
(1) Claims 5-12 and 20-25 stand rejected under 35 U.S.C. § 112, 2nd
paragraph, as being indefinite. Final Act. 7-8.
(2) Claims 5, 8-10, 12-15, and 17-20 stand rejected under
35 U.S.C. § 103(a) as being obvious over Baker and Drebin. Final Act. 9-16.
(3) Claims 6 and 7 stand rejected under 35 U.S.C. § 103(a) as being
obvious over Baker, Drebin, and Vangemert. Final Act. 16-17.
(4) Claim 11 stands rejected under 35 U.S.C. § 103(a) as being obvious
over Baker, Drebin, and Mang. Final Act. 17-18.
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Appeal2018-006827
Application 13/725,424
(5) Claims 16 and 24 stand rejected under 35 U.S.C. § 103(a) as being
obvious over Baker, Drebin, and Van Hook. Final Act. 18-19.
(6) Claim 21 stands rejected under 35 U.S.C. § 103(a) as being obvious
over Baker, Drebin, and Koegel. Final Act. 19-20.
(7) Claim 22 stands rejected under 35 U.S.C. § 103(a) as being obvious
over Baker, Drebin, and McCarthy. Final Act. 20-21.
(8) Claim 23 stands rejected under 35 U.S.C. § 103(a) as being obvious
over Baker, Drebin, and Jarvis. Final Act. 21.
(9) Claim 25 stands rejected under 35 U.S.C. § 103(a) as being obvious
over Baker, Drebin, and Eckart. Final Act. 22.
ISSUES
(1) Under§ 112, the dispositive issue is whether the Examiner has erred
in rejecting claims 5-12 and 20-25 as being indefinite because the Specification
fails to disclose corresponding structures that perform the claimed functions.
(2) Under§ 103, the dispositive issue is whether the Examiner has erred
in rejecting claims 5, 13, and 20 as being obvious over Baker and Drebin. In
particular, the issue turns on whether Baker discloses "blending unit is operable to
write the pixels from the blend buffer once for the plurality of texturing passes to
the frame buffer as a single write-only transaction on the frame buffer" as recited
in representative claim 1 (App. Br. 13) (emphasis added).
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Appeal2018-006827
Application 13/725,424
ANALYSIS
35 U.S.C. § 112, second paragraph
With respect to claims 5-12 and 20-25, the Examiner finds the term "unit"
recited in claim elements such as "texture read unit," "blending unit," and "control
unit" is indefinite under 35 U.S.C. § 112, second paragraph, because (1) there is no
corresponding structure disclosed in Appellant's Specification, and (2) the
"generalized description of a hardware pipeline" in Appellant's Specification does
not disclose specific structures performing the recited functions. Final Act. 7-8;
Ans. 23-25.
Appellant contends:
[t]o claim a means for performing a specific computer-implemented
function, the structure corresponding to the means-plus-function claim
limitation can be simply the algorithm needed to transform a general
purpose computer or microprocessor disclosed in the specification.
Aristocrat Techs. Australia Pty Ltd. V. Int 'l Game Tech., 521 F .3d
1328, 1333 (Fed. Cir. 2008); Finisar Corp. v. DirecTV Group, Inc.
523 F.3d 1323, 1340 (Fed. Cir. 2008); WMS Gaming, Inc. v. Int'!
Game Tech., 184 F.3d 1339, 1349 (Fed. Cir. 1999).
App. Br. 10. In particular, Appellant argues:
The present specification clearly provides the algorithms needed to
program a processor to carry out the claimed functions. See Figs. 2A.
2B and 6, as well the specific disclosures at pages 5-7.
Reply Br. 2.
We agree with Appellant. Under 35 U.S.C. § 112, sixth paragraph, the
"means-plus-function" limitation must be "construed to cover the corresponding
structure, material, or acts described in the specification and equivalents thereof."
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Application 13/725,424
Personalized Media Comm 'ns, LLC v. Int'! Trade Comm 'n, 161 F.3d 696, 703
(Fed. Cir. 1998). If the "means-plus-function" limitation recited in the claim does
not have an adequate supporting disclosure, then the claim fails to particularly
point out and distinctly claim the invention as required under 35 U.S.C. § 112,
second paragraph. See In re Donaldson Co., 16 F.3d 1189, 1195 (Fed. Cir. 1994)
("[I]f one employs means-plus-function language in a claim, one must set forth in
the specification an adequate disclosure showing what is meant . . . . If an
applicant fails to set forth an adequate disclosure, the applicant has in effect failed
to particularly point out and distinctly claim the invention as required by the
second paragraph of section 112.")
In the context of software, the disclosed structure is a general purpose
computer programmed to perform a disclosed algorithm. WMS Gaming, Inc. v.
Int'! Game Tech., 184 F.3d 1339, 1349 (Fed. Cir. 1999) ("In a means-plus-function
claim in which the disclosed structure is a computer, or microprocessor,
programmed to carry out an algorithm, the disclosed structure is not the general
purpose computer, but rather the special purpose computer programmed to perform
the disclosed algorithm."). A general purpose computer alone is insufficient if the
Specification fails to disclose an algorithm for performing the claimed function.
Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1367 (Fed. Cir. 2008).
Generic terms such as "mechanism," "element," "device," and other nonce
words used in a claim can also be considered as a substitute for the "means-plus-
function" limitation and, as such, may invoke the application of 35 U.S.C. § 112,
sixth paragraph, because these generic terms or nonce words "typically do not
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Application 13/725,424
connote sufficiently definite structure." Williamson v. Citrix Online, LLC, 792
F.3d 1339, 1350 (Fed. Cir. 2015) (en bane).
In this case, the correct analysis of claims 5-12 and 20-25 under 35 U.S.C.
§ 112, second paragraph, involves two questions: (1) whether the term "unit"
recited in claims 5-12 and 20-25 is used as a substitute for the "means-plus-
function" limitation and, as such, invokes the application of 35 U.S.C. § 112, sixth
paragraph; and (2) once the term "unit" is treated as a "means-plus-function"
limitation, whether Appellant's Specification discloses sufficient corresponding
structure, i.e., an algorithm for performing the functions recited in the "unit"
limitation. See Ex Parte Lakkala, Appeal 2011-001526 (PTAB March 13, 2013);
Williamson v. Citrix Online, LLC, 792 F.3d 1339 (Fed. Cir. 2015) (en bane). In
other words, Appellant's Specification must sufficiently disclose an algorithm to
transform the general purpose computer or processor to a special purpose processor
programmed to perform the disclosed algorithm. Aristocrat Techs. Australia Pty
Ltd. v. Int'! Game Tech., 521 F.3d 1328, 1338 (Fed. Cir. 2008). An algorithm is
defined, for example, as "a finite sequence of steps for solving a logical or
mathematical problem or performing a task." MICROSOFT COMPUTER DICTIONARY
23 (5th ed. 2002). An applicant may express the algorithm in any understandable
terms including as a mathematical formula, in prose, in a flow chart, or "in any
other manner that provides sufficient structure." Finisar Corp. v. DirecTV Group,
Inc., 523 F.3d 1323, 1340 (Fed. Cir. 2008).
An indefiniteness rejection under§ 112, second paragraph, is appropriate if
the Specification discloses no corresponding algorithm associated with a computer
or processor. Aristocrat, 521 F.3d at 1337-38. However, mere reference to a
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Appeal2018-006827
Application 13/725,424
general purpose computer or processor with appropriate programming without
providing an explanation of the appropriate programming, or to "software" without
providing detail about the means to accomplish the software function, is not an
adequate disclosure. Id. at 1334; Finisar, 523 F.3d at 1340-41. Likewise, simply
reciting the claimed function in the Specification, while saying nothing about how
the computer or processor ensures that those functions are performed, is not a
sufficient disclosure for an algorithm which, by definition, must contain a sequence
of steps. Blackboard, Inc. v. Desire2Learn, Inc., 574 F.3d 1371, 1384 (Fed. Cir.
2009).
In this case, we agree with the Examiner that the term "unit" recited in
claims 5-12 and 20-25 is a generic term which invokes the application of 35
U.S.C. § 112, sixth paragraph. However, we find Appellant's Specification
sufficiently discloses an algorithm in the context of Figure 7 as well as Figures 2A,
2B and 6, as Appellant argues. Reply Br. 2. Separately, we find the terms "on the
graphics chip," in "a texture read unit on the graphics chip," "a blending unit on
the graphics chip," and "control unit on the graphics chip," recited in Appellant's
claims clearly indicate that these units are circuitry, thus providing hardware
structures.
For these reasons, we do not sustain the Examiner's rejection of claims 5-12
and 20-25, under 35 U.S.C. § 112, second paragraph.
35 U.S.C. § 103(a)
With respect to claims 5, 13, and 20, the Examiner finds Baker discloses
Appellant's claimed "3-D graphics system" shown in Figure 5A including the
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Application 13/725,424
disputed limitation: "blending unit is operable to write the pixels from the blend
buffer once for the plurality of texturing passes to the frame buffer as a single
write-only transaction on the frame buffer" ( claim 5) and, similarly, "writing the
results of the plurality of texture blending operations once for the plurality of
texture blending operations to a frame buffer in a single write-only transaction"
(claims 13 and 20). Final Act. 9-16 (citing Baker,i,i 27, 66, Fig. 5A).
Baker's Figure 5A is reproduced below with additional markings for
illustration.
frarne b uHer
flG. 5-A
10
TEXTURE CACHE 94
TEXW!:iE MA?
:i~,~
.. ..
TEX"fURE MAP
iin
Appeal2018-006827
Application 13/725,424
As shown in Figure 5A, Baker's pipeline utilizes destination frame buffer
98a to store destination pixel data and temporary frame buffer 98b to store
temporary data from the passes. Baker ,i 66.
In particular, the Examiner finds that Baker "clearly show[ s] that the pixels
are written from the blend buffer once after the texture passes occur" and that
"operations are described as enabling a 'write to one frame buffer per pixel'
(section 0066), meaning that when pixels are written to the destination frame
buffer, they are written as a single write-only operation, rather than an operation
involving multiple writes to multiple frame buffers." Ans. 27-28.
Appellant contends Baker does not disclose that the "blending unit is
operable to write the pixels from the blend buffer once for the plurality of texturing
passes to the frame buffer as a single write-only transaction on the frame buffer"
(claim 5) and, similarly, "writing the results of the plurality of texture blending
operations once for the plurality of texture blending operations to a frame buffer in
a single write-only transaction" ( claims 13 and 20). Reply Br. 4-7, App. Br. 13-
14. In particular, Appellant argues "Baker teaches that data in a destination frame
buffer is modified to blend texture maps, to blend pixel data with results of
texturing passes, and to perform alpha blending," which indicates that "writing of
data to the frame buffer in Baker is not performed 'as a single write-only
operation' as recited in the present claims." App. Br. 14.
In response, the Examiner takes the position that "claims do not require that
the only transaction ever performed be a single write-only transaction" and that no
"[ o ]ther transactions can be performed during other operations in Baker while still
teaching the claim." Ans. 28.
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Application 13/725,424
We find the Examiner's position reasonable. For example, during initial
pass, the "blending units 93 store the texture value (e.g., R, G, B color values)
associated with the texture coordinates in a temporary frame buffer, such as
temporary frame buffer 98b." Baker ,-J 68. In the second texture pass, "blending
units 93 blend the texture values for the pixel obtained in the first pass and stored
in the temporary frame buffer 98b with the texture value for the pixel obtained in
the current pass." Baker ,-J 69. In the third and final texture pass, the "blending of
the values results in composite texture values that include the texture values
obtained from all three passes and is then optionally further blended by the
blending units 93 with the destination pixel data stored in the destination frame
buffer 98a." (emphasis added) Baker ,-J 70.
In other words, destination pixel data stored in the destination frame buffer
may not be subject to further modification, but is a new final current data to be
displayed as Baker discloses that destination pixel data is "the current destination
pixel data." Baker ,-J 7. If the current destination pixel data needs to be modified
with the composite texture values that are resultant values from the texturing
passes, then such data will be stored in the destination frame buffer in a single
write-only transaction as final data to be displayed. Baker ,-J 70. Because Baker's
Figure 5A shows a destination frame buffer 98a that stores current destination
pixel data and a temporary frame buffer 98b that stores the temporary data, a
skilled artisan would understand that the new pixel data to be displayed is written
on the destination frame buffer as a new current destination pixel data. However,
we note that Baker teaches the concept of "single write-only transaction on the
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frame buffer" before data can be displayed in the context of Figure 1, as
reproduced below with additional markings for illustration.
FH1, 1
{PJUOR ART}
As shown in Baker's Figure 1, each texture unit 15 includes texture cache 16
and texture blender 17. Each texture unit "receives the series of texture
coordinates set for the pixel" the previous texture unit and the texture blender
performs a blending operation, which includes blending the texture values
corresponding to texture coordinates from the previous texture maps. Baker ,i,i 13-
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16. Baker also teaches that after texturing, the pixels are optionally modified by
the destination blender 18, which applies further blending to the pixels that are
then mapped to a frame buffer 19. Baker ,i 18. In other words, the resulted pixels
of the blending operation is written in the frame buffer, and that when the pixels
are written to the frame buffer, it is written once as a single write-only transaction
as there is no further modification to be made.
For these reasons, we agree with the Examiner that Baker teaches the
disputed limitation of Appellant's claims 5, 13, and 20. Accordingly, we sustain
the Examiner's obviousness rejection of independent claims 5, 13, and 20, and
their respective dependent claims 6-12, 14-19, and 21-25 which Appellant does
not argue separately. App. Br. 15. However, because we have relied on facts and
reasoning not raised by the Examiner, we designate our affirmance as a new
ground of rejection pursuant to 37 C.F.R. § 41.50(b) to preserve Appellant's
procedural safeguards. In re Stepan Co., 660 F.3d 1341, 1346 (Fed. Cir. 2011)
("Had the Board labeled its rejection as a new ground of rejection, Stepan could
have reopened prosecution to address the newly-alleged deficiencies in its
Declaration with the examiner."); In re Leithem, 661 F.3d 1316, 1319 (Fed. Cir.
2011) ("Mere reliance on the same statutory basis and the same prior art
references, alone, is insufficient to avoid making a new ground of rejection when
the Board relies on new facts and rationales not previously raised to the applicant
by the examiner.").
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Application 13/725,424
CONCLUSION
On the record before us, we conclude that Appellant has demonstrated that
that the Examiner erred in rejecting claims 5-12 and 20-25 as being indefinite
under 35 U.S.C. i]l 12, 2nd paragraph. However, we conclude Appellant has not
demonstrated the Examiner erred in rejecting claims 5-25 under 35 U.S.C.
§ 103(a).
DECISION
As such, we AFFIRM the Examiner's final rejection of claims 5, 8-10, 12-
15, and 17-20 under 35 U.S.C. § 103(a) over Baker and Drebin, and designate our
affirmance as a new ground of rejection pursuant to 37 C.F.R § 41.50(b) to
preserve Appellant's procedural safeguards because we have relied on facts and
reasoning not raised by the Examiner.
Rule 37 C.F.R. § 41.50(b) states that "[a] new ground of rejection pursuant
to this paragraph shall not be considered final for judicial review." Further,
§ 41.50(b) also provides that Appellant, WITHIN TWO MONTHS FROM THE
DATE OF THE DECISION, must exercise one of the following two options with
respect to the new grounds of rejection to avoid termination of the appeal as to the
rejected claims:
(1) Reopen prosecution. Submit an appropriate amendment of the
claims so rejected or new [ e ]vidence relating to the claims so rejected,
or both, and have the matter reconsidered by the examiner, in which
event the prosecution will be remanded to the examiner ....
(2) Request rehearing. Request that the proceeding be reheard under
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§ 41.52 by the Board upon the same record .... No time period for taking any
subsequent action in connection with this appeal may be extended under 37 C.F.R.
§ l.136(a)(l )(iv).
AFFIRMED; 37 C.F.R. § 41.50(b)
16