Ex Parte Berenbaum

Patent Trial and Appeal Board

Oct 18, 2017

13004890 (P.T.A.B. Oct. 18, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/004,890 01/12/2011 ALAN BERENBAUM 68354.227217 1409
86528 7590 10/20/2017
Slay den Grubert Beard PLLC
401 Congress Avenue
Suite 1900
Austin, TX 78701
EXAMINER
ZAMAN, FAISAL M
ART UNIT PAPER NUMBER
2185
NOTIFICATION DATE DELIVERY MODE
10/20/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
trosson @ sgbfirm.com
patent @ sgbfirm. com
dallen @ sgbfirm. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ALAN BERENBAUM
Appeal 2015-002657
Application 13/004,890
Technology Center 2100
Before JOSEPH L. DIXON, MONICA S. ULLAGADDI, and
SCOTT B. HOWARD, Administrative Patent Judges.
DIXON, Administrative Patent Judge.
DECISION ON APPEAL
Appeal 2015-002657
Application 13/004,890
STATEMENT OF THE CASE
Appellant1 appeals under 35 U.S.C. § 134(a) from a rejection of
claims 1—22. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
The claims are directed to a method and system for implementing bus
operations with precise timing. Claim 1, reproduced below, is illustrative of
the claimed subject matter:
1. A system for implementing bus operations with precise
timing, the system comprising:
a processor;
a system bus operable to receive read and write operations;
a trigger descriptor register for defining a bus operation to
be performed on said system bus, the trigger descriptor register
including:
i. a bus definition field including data and
address fields, configured for providing prewritten data
and address information for executing the bus operation;
and
ii. a trigger select field configured to select a
trigger signal for the bus operation wherein the trigger
signal triggers a hardware assisted execution of the bus
operation without control of any processor, thereby
transmitting said prewritten data and address information
over the system bus; and
wherein the processor is operable to configure the trigger
descriptor register.
1 Appellant indicates that Standard Microsystems Corporation is the real
party in interest. (App. Br. 2.)
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Appeal 2015-002657
Application 13/004,890
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Fukuichi US 4,152,887 May 8, 1979
Gulick US 5,898,848 Apr. 27, 1999
Douskey et al. US 6,115,763 Sept. 5, 2000
(hereinafter “Douskey”)
Suzuki et al. US 2001/0005870 Al June 28, 2001
(hereinafter “Suzuki”)
Klassen et al. US 6,351,724 B1 Feb. 26, 2002
(hereinafter “Klassen”)
Marr et al. US 2002/0194409 Al Dec. 19, 2002
(hereinafter “Marr”)
Agarwal US 2007/0198759 Al Aug. 23, 2007
REJECTIONS
The Examiner made the following rejections:
Claims 20-22 stand rejected under 35 U.S.C. § 112 (pre-AIA), first
paragraph, as failing to comply with the written description requirement.
The claims contain subject matter which was not described in the
specification in such a way as to reasonably convey to one skilled in the
relevant art that the inventor or a joint inventor, or for pre-AIA the
inventor(s), at the time the application was filed, had possession of the
claimed invention.
Claims 1,9, 10, and 20-22 stand rejected under pre-AIA 35 U.S.C.
§ 103(a) as being unpatentable over Marr and Gulick.
Claims 2 and 6—8 stand rejected under pre-AIA 35 U.S.C. § 103(a) as
being unpatentable over Marr and Gulick as applied to claim 1, and further
in view of Klassen.
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Application 13/004,890
Claim 3 stands rejected under pre-AIA 35 U.S.C. § 103(a) as being
unpatentable over Marr, Gulick, and Klassen as applied to claim 2, and
further in view of Suzuki.
Claim 4 stands rejected under pre-AIA 35 U.S.C. § 103(a) as being
unpatentable over Marr and Gulick as applied to claim 1, and further in view
of Fukuichi.
Claim 5 stands rejected under pre-AIA 35 U.S.C. § 103(a) as being
unpatentable over Marr and Gulick as applied to claim 1, and further in view
of Douskey.
Claims 11, 18, and 19 stand rejected under pre-AIA 35 U.S.C.
§ 103(a) as being unpatentable over Marr and Agarwal.
Claims 12 and 15 stand rejected under pre-AIA 35 U.S.C. § 103(a) as
being unpatentable over Marr and Agarwal as applied to claim 11, and
further in view of Klassen and Suzuki.
Claim 13 stands rejected under pre-AIA 35 U.S.C. § 103(a) as being
unpatentable over Marr and Agarwal as applied to claim 11, and further in
view of Fukuichi.
Claim 14 stands rejected under pre-AIA 35 U.S.C. § 103(a) as being
unpatentable over Marr and Agarwal as applied to claim 11, and further in
view of Douskey.
Claims 16 and 17 stand rejected under pre-AIA 35 U.S.C. § 103(a) as
being unpatentable over Marr and Agarwal as applied to claim 11, and
further in view of Klassen.
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Application 13/004,890
ANALYSIS
35 U.S.C. § 112, first paragraph, written description
The Examiner maintains that the claimed “wherein the system bus
comprises data, address, and control lines” lacks written description support
in the originally filed Specification. (Final Act. 2—3.)
Appellant contends:
"The system 100 is capable of performing a bus
transaction (read or write) over an internal system bus 102, such
as an Advanced Performance Bus (AHB)."
(Specification, par. [0014]). A person skilled in the art
will understand that the internal system bus must have data,
address and control lines. The term "system bus", in particular
"internal system bus", in embedded systems or processors is well
known in the art. It describes the central communication path
that allows for the processor to communicate with memory and
peripheral devices. To this end, it requires at a minimum, data,
address, and control lines. Hence, these limitations are at a
minimum implied.
Moreover, the specification provides for an example for
such an internal system bus, namely an Advanced High-
performance Bus (AHB). (Id.) The Advanced High-
performance Bus has been developed by ARM Ltd and is an open
standard [u]nder the Advanced Microcontroller Bus
Architecture. Hence, the AHB is well established in the field of
embedded system. It describes one type of internal bus system
that allows read and write transactions between devices using
data, address, and control lines according to a defined protocol.
Numerous documentations of this bus type is available to the
person skilled in the art and Appellant[] believes that it is not
necessary to provide additional extrinsic evidence to prove that
an internal system bus comprises at least data, address and
control lines.
(App. Br. 6.)
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The Examiner bases the finding of lack of written description support
on “the fact that the originally-filed Specification does not state that the
claimed ‘system bus’ comprises data, address, and control lines.” (Ans. 2.)
The test for written description is summarized in Purdue Pharma L.P.
v. FauldingInc., 230 F.3d 1320 (Fed. Cir. 2000):
In order to satisfy the written description requirement, the
disclosure as originally filed does not have to provide in haec
verba support for the claimed subject matter at issue.
Nonetheless, the disclosure must . . . convey with reasonable
clarity to those skilled in the art that . . . [the inventor] was in
possession of the invention. Put another way, one skilled in the
art, reading the original disclosure, must immediately discern the
limitation at issue in the claims. That inquiry is a factual one and
must be assessed on a case-by-case basis.
Purdue, 230 F.3d at 1323 (alterations in original) (citations omitted).
Contrary to the stated position of the Examiner, there is no word for
word or “ipsis verbis” requirement for the written description portion of 35
U.S.C. § 112, first paragraph. See Union Oil Co. of Cal. v. Atl. Richfield
Co., 208 F.3d 989, 1000 (Fed. Cir. 2000) (The invention claimed does not
have to be described in ipsis verbis in order to satisfy the written description
requirement.).
We disagree with the Examiner and find that Appellant’s
Specification, as originally filed, evidences possession of the invention of
claims 20—22 at the time of the original filing date. Although Appellant’s
Specification does not expressly include the language of the claim, we find
the Specification conveys “with reasonable clarity to those skilled in the art
that. . . [the inventor] was in possession of the invention. Put another way,
one skilled in the art, reading the original disclosure, must immediately
discern the limitation at issue in the claims.” Purdue, 230 F.3d at 1323
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(alteration in original) (citation omitted). As a result, we cannot sustain the
lack of written description support rejection of claims 20—22.
35U.S.C. § 103
Claims 1, 3—10, 20, and 21
Appellant argues the claims together. (App. Br. 8.) We select
independent claim 1 as the representative claim for the group and address
Appellant’s arguments thereto.
With respect to representative independent claim 1, Appellant
contends that the Examiner erred in concluding that the Marr reference
discloses a system bus as claimed. Specifically, Appellant contends that
lines 122(a)-112(d) are interrupt lines used to communicate an
interrupt to the CPU. Interrupt lines are well known in the art.
They are use[d] to forward interrupt signal which when asserted
interrupt a current processing and force the processor to execute
an interrupt service routine. Upon execution of such a service
routine, the processor continues and jumps back to the point at
which it was interrupted. This type of operation is exactly what
the present application tries to avoid. (Specification, par.
[0005]). Moreover, interrupt lines are not configured to allow
read or write operations. They are not designed to perform such
a function and their main and only purpose is to signal an event
to the central processing unit.
(App. Br. 8.) Appellant generally contends that the interrupt lines of the
Marr reference are not a system bus. We disagree with Appellant wherein
Appellant has not identified any limiting context or claim limitations with
which to distinguish independent claim 1.
The Examiner maintains that:
Contrary to Appellant's, Marr does in fact disclose the argued
features. More specifically, item 518 within register 510
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provides "data" as to which CPU line 112 is to be used, while
item 514 within register 510 provides an "address" (i.e., the
address of the interrupt source). Accordingly, it can be seen that
Marr does in fact disclose the argued features.
(Ans. 3.)
The Examiner further maintains:
However, the argued claims do not require the "bus operation" to
be a read or write bus operation, as Appellant has argued. In
response to applicant's argument that the references fail to show
certain features of applicant's invention, it is noted that the
features upon which applicant relies (i.e., the bus operation is a
read or write bus operation) are not recited in the rejected
claim(s). Although the claims are interpreted in light of the
specification, limitations from the specification are not read into
the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d
1057 (Fed. Cir. 1993). As stated in the Final Office action, the
examiner had interpreted the execution of an interrupt handler as
equivalent to the claimed "bus operation". Accordingly, it can
be seen that Marr does in fact disclose the argued feature.
(Ans. 3—4.) We agree with the Examiner that independent claim 1 does not
require performing a read or write operation, but merely recites “transmitting
said prewritten data and address information over the system bus.” The
Examiner further finds:
Contrary to Appellant’s argument, Marr does in fact disclose the
argued feature. The claims requires that it is the trigger signal
that triggers . . . the bus operation without control of any
processor" (as recited in Claim 1, and similarly in Claim 20). As
stated in the Final Office action, trigger module 424 triggers
execution (i.e., the claimed “trigger signal”) of the bus operation
without control of CPU 114.
(Ans. 4.) We agree with the Examiner that Appellant’s arguments are not
commensurate in scope with the express language of independent claim 1
and therefore do not show error in the Examiner’s factual findings or
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conclusion of obviousness. Additionally, we find that Appellant merely
argues the Marr reference and not the combination as set forth by the
Examiner in the grounds of the rejection. Consequently, Appellant’s
arguments do not show error in the Examiner’s factual findings or
conclusion of obviousness of representative independent claim 1 and its
respective dependent claims 9 and 10. Because Appellant has not set forth
separate arguments for patentability of dependent claims 3—8, independent
claim 20, and dependent claim 21, we group these claims as falling with
representative independent claim 1.
Claims 11—19
With respect to claims 11—19, Appellant has not set forth separate
arguments for patentability of each of the claims, and we select independent
claim 11 as the representative claim for the group.
With respect to representative independent claim 11, the Examiner
further finds:
it is unclear as to how Appellant is interpreting the claimed “bus
operation”. As stated in the Final Office action, the examiner
had interpreted execution of an interrupt handler as equivalent to
the claimed “bus operation”. Accordingly, it can be seen that
both Marr and Agarwal do in fact disclose the claimed “bus
operation.”
(Ans. 4.) In response to Appellant’s argument that “Agarwal does not teach
the step of performing the bus operation based on the address and data fields
without processor intervention” (App. Br. 11), the Examiner further finds
“Agarwal teaches that the bus operation (i.e., handling the interrupt) can be
performed without the intervention of main processor 17. Accordingly, the
teachings of Agarwal meet the argued claim limitation.” (Ans. 5.) We agree
with the Examiner. We further note that the Examiner had relied upon the
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Marr reference for teaching the performance of the bus operation, and the
Agarwal reference for teaching “without intervention of the main
processor.” (Final Act. 12; Ans. 5.) We agree with the Examiner that the
interrupt handling processor 10 will process of the interrupt without the
intervention of the main processor 17. (Agarwal, 129). As a result,
Appellant’s argument does not show error in the Examiner’s factual findings
or the conclusion of obviousness of representative independent claim 11.
Appellant has not set forth separate arguments for patentability of dependent
claims 12—19. As a result, we sustain the obviousness rejections of claims
12—19 for the same reasons as representative independent claim 11.
Dependent claims 2 and 22
With respect to dependent claims 2 and 22, Appellant repeats the
language of the claim and generally contends that the additional prior art
reference or official notice is improper. (App. Br. 11—12.) Appellant’s
contention amounts to a general denial that fails to address the Examiner’s
findings and is, therefore, insufficient to be considered an argument for
separate patentability. See 37 C.F.R. § 41.37(c)(l)(iv) (“A statement which
merely points out what a claim recites will not be considered an argument
for separate patentability of the claim.”); In reLovin, 652 F.3d 1349, 1357
(Fed. Cir. 2011) (“[W]e hold that the Board reasonably interpreted Rule
41.37 to require more substantive arguments in an appeal brief than a mere
recitation of the claim elements and a naked assertion that the corresponding
elements were not found in the prior art.”). As a result, Appellant’s
argument does not show error in the Examiner’s factual findings or the
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conclusion of obviousness, and we sustain the obviousness rejections of
dependent claims 2 and 22 for the same reasons as their parent claims.
Reply Brief
We find the Examiner has responded to each of Appellant’s
contentions by clarifying the claim interpretation and application of the prior
art references. Appellant continues to contend that the Examiner has failed
to present any arguments as to why a person of ordinary skill in the art
would interpret the term “system bus” simply as lines connecting
components of the system. (Reply Br. 7.) We disagree with Appellant and
find that Appellant has not identified how the Specification or claim
language specifically defines the structure of “system bus” so as to
differentiate from the applied prior art references. Moreover, we find that
the Marr reference teaches and suggests the use of a MIPS processor which
has multiple registers which are shown in Figures 5 through 12 which would
hold both data and instructions subject to the control of the interrupt lines
112(aHd).
Appellant further contends that:
Claim 1 particularly] includes the limitation that data and
address information is transmitted over the system bus. Selecting
a signal line and selecting a source are not equivalent to
transmitting data and address over a system bus. Marr fails to
disclose that items 518 and 514 are actually transmitted in any
form over the alleged system bus consisting of lines 112(a)-(d)
and 412 according to the Examiner's interpretation.
(Reply Br. 8.) We disagree with Appellant. Appellant further argues:
Hence, contrary to the statement made on page 4, lines 4-12 of
the Examiner's Answer, the Examiner admits that according to
his interpretation the bus operation is equivalent to the execution
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of an interrupt handler. The interrupt handler is the instruction
routine executed once an interrupt has been received. It is well
known in the art that it is the processor which receives the
interrupt signal that executes this interrupt handler. Hence, the
Examiner contradicts himself. Marr teaches away from the
claimed subject matter by using an interrupt handler executed by
the processor to perform a bus operation.
(Reply Br. 9.) We disagree with Appellant and find the language of claim 1
sets forth a system for implementing bus operations with precise timing the
system having a processor, a system bus which includes two fields, and the
processor is operable to configure the trigger description register, but find
that the claim does not recite the details of how the processor configures the
register.
We find Appellant’s arguments merely address the disclosure of the
Marr reference and does not address the merits of the rejection as proffered
by the Examiner. Consequently, Appellant’s arguments does not show error
in the Examiner’s factual findings or conclusion of obviousness.
CONCLUSION
The Examiner erred in rejecting claims 20—22 based upon failing to
comply with the written description requirement under 35 U.S.C. § 112 (pre-
AIA), first paragraph.
The Examiner did not err in rejecting claims 1—22 based upon
obviousness under 35 U.S.C. § 103.
DECISION
For the above reasons, we sustain the Examiner’s rejection of claims
1—22 based upon obviousness under 35 U.S.C. § 103.
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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