Ex Parte Benjamin

Patent Trial and Appeal Board

Aug 11, 2016

12008851 (P.T.A.B. Aug. 11, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/008,851 01115/2008
22879 7590 08/15/2016
HP Inc,
3390 E. Harmony Road
Mail Stop 35
FORT COLLINS, CO 80528-9544
FIRST NAMED INVENTOR
Trudy Benjamin
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
82209800 2309
EXAMINER
HUFFMAN, TIJLIAN D
ART UNIT PAPER NUMBER
2853
NOTIFICATION DATE DELIVERY MODE
08/15/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ipa.mail@hp.com
barbl@hp.com
yvonne.bailey@hp.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte TRUDY BENJAMIN1
Appeal2015-003033
Application 12/008,851
Technology Center 2800
Before: ROMULO H. DELMENDO, CHRISTOPHER C. KENNEDY, and
LILAN REN, Administrative Patent Judges.
REN, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134 from a rejection2 of claims
22-24, 32, 33, and 35. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
1 The real party in interest is identified as Hewlett-Packard Development
Company, LP which is said to be a wholly-owned affiliate of Hewlett-
Packard Company. (Appeal Brief, filed September 15 2014 ("App. Br."), 3.)
2 Final Office Action mailed April 15 2014 ("Final Rejection"; cited as
"FR.").
Appeal2015-003033
Application 12/008,851
CLAIMED SUBJECT MATTER
The subject matter on appeal relates to using "electronically
programmable read-only memory, or EPROM" to "eliminate fuses in
NMOS circuits, such as in inkjet printheads and other applications." (Spec.
3, 11. 26-28.)3
Claim 22, reproduced below, is illustrative of the claimed subject
matter:
22. A memory cell of an ink jet printhead circuit having a
semiconductor substrate, a first dielectric layer disposed atop the
substrate, a semiconductive polysilicon layer disposed atop the
first dielectric layer, a first metal layer disposed above the
polysilicon layer, a second dielectric layer disposed atop the first
metal layer, and a second metal layer disposed atop the second
dielectric layer, the memory cell comprising an EPROM cell,
wherein:
the semiconductor substrate includes source and drain
reg10ns;
the second dielectric includes materials selected from the
group consisting of silicon carbide and silicon nitride;
the semiconductor substrate and the polysilicon layer are
configured and unvaryingly spaced apart to transfer charge from
the semiconductor substrate to the polysilicon layer via hot
carrier injection in the EPROM cell;
the polysilicon layer and the first metal layer are
electrically interconnected and comprise a floating gate
configured to control a flow of current between the source and
drain regions; and
the second metal layer is situated over the first metal layer
to capacitively couple the second metal layer to the first metal
layer through the second dielectric layer and the second metal
layer comprises a control gate.
(Claim Appendix, App. Br. 10 (emphases added).)
3 Application 12/008,851, Modified-Layer EPROM Cell, filed January 15
2008. We refer to the '" 851 Specification," which we cite as "Spec."
2
Appeal2015-003033
Application 12/008,851
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Murray
Eldridge
US 5,610,635 Mar. 11, 1997
US 2004/0159863 Al Aug. 19, 2004
REJECTIONS
Claims 22-24, 32, 33, and 35 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over Murray and Eldridge. (FR. 2.)
OPINION
Findings of fact throughout this Opinion are supported by a
preponderance of the evidence of record.
The Examiner rejects claim 224 finding that Murray discloses "an ink
jet printhead" whereas Eldridge discloses a "memory cell comprising an
EPROl\1 cell" having the limitations recited in claim 22. (FR. 2-3.) l\1ore
specifically, the Examiner cites to Figure 2 of Eldridge which is reproduced
below:
4 Appellant does not argue claims 23, 24, 32, 33, and 35 separately and,
therefore, these claims stand or fall with claim 22. (App. Br. 4-8.)
3
Appeal2015-003033
Application 12/008,851
201
FIG. 2
200
217
/
·2Hi
209
FIG. 2 of Eldridge illustrating a "non-volatile memory cell." Cii 47.)
As illustrated in Figure 2, "non-volatile memory cell 200" includes
"substrate 206." (Eldridge ii 76.) Gate oxide 211 (i.e., a first dielectric
layer) is disposed on top of substrate 206. (Id; see also FR. 3.) Memory cell
200 also includes "floating gate 209" that "includes a polysilicon floating
gate 209 having a metal layer 216 formed thereon in contact with the graded
composition metal oxide tunnel barrier integrate insulator 215" (i.e., a
second dielectric layer). (Eldridge ii 76; see also FR. 3.) The "control gate
213 includes a polysilicon control gate 213 having a metal layer 217."
(Eldridge ii 76.)
Appellant does not refute the Examiner's findings regarding these
prior art teachings and in fact acknowledges that "the control gate 213
includes polysilicon control gate 23 having a metal layer 217 formed
thereon" in Eldridge. (App. Br. 7.) Appellant, however, argues that the
"polysilicon control gate 213 is formed on top of metal layer 217" in
4
Appeal2015-003033
Application 12/008,851
Eldridge and therefore "metal layer 217 ... does not comprise a control gate
as required by independent claim 22." (Id.)
Claim 22, as it is currently written, does not recite a particular type of
association (e.g., spatial or otherwise) between a "second layer" and "a
control gate." Appellant does not propose a particular construction of the
claim term a "second metal layer [that] comprises a control gate." (See, e.g.,
App. Br. 6-8; Reply 2-3.)5 Appellant does not point to a particular
embodiment in the Specification showing a memory cell having a "second
metal layer [that] comprises a control gate" as recited in claim 22. Appellant
does not explain why the Examiner erred in finding that the prior art "control
gate includes a polysilicon layer and a metal layer." (Ans. 3.) 6 Appellant
does not explain why a "second metal layer [that] comprises a control gate"
as recited in claim 22 is patentably distinguished from the prior art "control
gate 23" which includes "polysilicon control gate 23 having a metal layer
217 formed thereon." (See, e.g., App. Br. 6-8; Reply 2-3.) No reversible
error has been identified in this aspect of the obviousness analysis.
Appellant next argues that the Examiner erred because Eldridge does
not teach or suggest a memory cell having a "second dielectric [that]
includes materials selected from the group consisting of silicon carbide and
silicon nitride" as recited in claim 22. (App. Br. 7-8; Reply 2-3.)
The Examiner, on the other hand, finds that Eldridge teaches a tunnel
barrier which is a dielectric - a finding that is unrefuted by Appellant. (Ans.
4; see Reply 2-3.) The Examiner also finds that Eldridge teaches that
"graded tunnel barriers comprised of other insulating materials including
5 Reply Brief filed January 21 2015 ("Reply").
6 Examiner's Answer mailed November 21 2014 ("Ans.").
5
Appeal2015-003033
Application 12/008,851
oxy-nitrides, nitrites and possibly oxy-carbides and even carbides" may be
used in the "oxide tunnel barrier structures" such as the insulator 215 shown
in Figure 2. (Ans. 4 (citing Eldridge iJ 111).) Eldridge also shows SbN4 as
an example of an oxide barrier in Table A and that "SiC gate insulators" is
known in the prior art. (Eldridge iii! 7, 110; FIG. IA.)
Appellant does not explain why a skilled artisan would not have found
the recited "silicon carbide and silicon nitride" for a "dielectric" a predicable
result based on the prior art teaching of using "nitrites and possibly oxy-
carbides and even carbides" as insulating material. (See Eldridge iJ 111.)
Appellant does not explain why this limitation is patentably distinguished
from the SbN4 and SiC used in EPROM cells expressly disclosed in
Eldridge. (See id. iii! 7, 110; FIG. IA.) The '851 Specification appears to
provide no more than a single statement that the "inventor has used a silicon
carbide/silicon nitride material for the dielectric layer[.]" (Spec. 6, 11. 16-
18.) No reversible error has therefore been identified in this aspect of the
obviousness analysis. See KSR Int 'l Co. v. Teleflex Inc., 550 U.S. 398, 417
(2007) ("If a person of ordinary skill can implement a predictable variation
[of a known work],§ 103 likely bars its patentability.").
DECISION
The Examiner's rejection of claims 22-24, 32, 33, and 35 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § l.136(a). See 37 C.F.R.
§ l.136(a)(l )(iv).
AFFIRMED
6