Ex Parte Belot

Patent Trial and Appeal Board

Sep 20, 2013

11820495 (P.T.A.B. Sep. 20, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte DIDIER BELOT
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Appeal 2013-007429
Application 11/820,495
Technology Center 2800
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Before DEBORAH KATZ, JACQUELINE WRIGHT BONILLA, and
HUNG H. BUI, Administrative Patent Judges.

BUI, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 seeks our review under 35 U.S.C. § 134(a) of the
Examiner’s final rejection of claims 1-20. We have jurisdiction under 35
U.S.C. § 6(b).
We AFFIRM.2

1 Real Party in Interest is STMicroelectronics SA.
2 Our decision refers to Appellant’s Appeal Brief filed February 19, 2013
(“App. Br.”); Reply Brief filed May 20, 2013 (“Reply Br.”); Examiner’s
Answer mailed March 19, 2013 (“Ans.”); Final Office Action mailed August
21, 2012 (“FOA”); and the original Specification filed June 19, 2007
(“Spec.”).
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STATEMENT OF THE CASE
Appellant’s Invention
Appellant’s invention relates to integrated circuits (ICs) having a low-
noise amplifier powered by a current controlled by a transistor. See Spec.,
¶[0002]. According to Appellant, the transistor is disposed inside a
semiconductor well of a silicon-on-insulator (SOI) type, shown in FIG. 3,
such that an output current of such a transistor can be controlled by varying
or adjusting the value of a bias voltage applied to the well. Id., ¶¶[0039]-
[0041].
FIG. 3 is reproduced below:

FIG. 3 shows Appellant’s transistor of a SOI type.
As shown in FIG. 3, the transistor 204 of a SOI type includes a source
terminal 310 and a drain terminal 312 of n+ type conductivity; a gate
electrode 304 formed on a semiconductor well 302 of p- type conductivity
between the source terminal 310 and the drain terminal 312; an oxide layer
306 disposed between the gate electrode 304 and the semiconductor well
302; spacers 308a-308b formed on either side of the gate electrode 304; and
a contact region 314 of p+ type conductivity formed adjacent to the source
terminal 310 in contact with the semiconductor well 302 coupled to ground,
via on an insulating layer 316. Id., ¶¶[0022]-[0024].
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Claims on Appeal
Claims 1, 9, and 15 are the independent claims on appeal. Claim 1 is
illustrative of Appellant’s invention, and is reproduced below with disputed
limitations emphasized and some paragraphing added:

1. A method of controlling an output current of a
transistor disposed inside a semiconductor well, the method
comprising:
selectively turning the transistor on by setting a gate
voltage applied to a gate of the transistor; and
adjusting a bias voltage of the semiconductor well to
selectively reduce the transistor output current when the
transistor is turned on,
wherein the bias voltage is adjusted using an input signal
received at a heavily doped contact region positioned within the
well adjacent to a source,
wherein both a threshold voltage of the transistor and the
transistor output current in response to the gate voltage are
dependent upon and changed by adjustments to the bias
voltage,
wherein the semiconductor well is coupled to a ground
through an insulating layer, and
wherein the contact region, the source, and a drain are in
contact with the semiconductor well.

Evidence Considered
Chandrakasan U.S. 6,967,522 B2 Nov. 22, 2005
Koch U.S. 6,404,243 B1 Jun. 11, 2002
Meng U.S. 6,418,040 B1 Jul. 9, 2002
Teraoka U.S. 6,333,571 B1 Dec. 25, 2001

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Application 11/820,495

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Examiner’s Rejections
(1) Claims 1-20 stand rejected under 35 U.S.C. § 112, 1st
paragraph, as failing to comply with the written description requirement.
FOA 2.
(2) Claims 1-20 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Chandrakasan and Meng. FOA 2-4.
(3) Claims 1-20 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Koch, Chandrakasan, and Meng. FOA 4-6.

Issues on Appeal
Based on Appellant’s arguments, the dispositive issues on appeal are:
(1) Whether the Examiner erred in rejecting claims 1-20 under 35
U.S.C. §112, 1st paragraph, for failing to comply with the written description
requirement. In particular, the issue turns on whether Appellant’s original
Specification describes “adjusting a bias voltage of the semiconductor well
to selectively reduce the transistor output current when the transistor is
turned on,” as recited in independent claims 1, 9, and 15 (emphasis added).
(2) Whether the Examiner erred in rejecting claims 1-20 under 35
U.S.C. § 103(a) as being unpatentable over Chandrakasan and Meng. In
particular, the issue turns on whether the combination of Chandrakasan and
Meng discloses or suggests all limitations of independent claims 1, 9, and
15.
(3) Whether the Examiner erred in rejecting claims 1-20 under 35
U.S.C. § 103(a) as being unpatentable over Koch, Chandrakasan, and Meng.
The issue turns on whether the combination of Koch, Chandrakasan, and
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Meng discloses or suggests all limitations of independent claims 1, 9, and
15.

ANALYSIS
§ 112, 1st Paragraph Rejection of Claims 1-20
The Examiner finds Appellant’s original specification fails to disclose
“adjusting a bias voltage of the semiconductor well to selectively reduce the
transistor output current when the transistor is turned on.” FOA 2
(emphasis added).
Appellant contends that the original Specification teaches that the
transistor is turned on as the bias voltage varies between its minimum to
maximum values to adjust the transistor output current. App. Br. 11-12
(citing Spec., ¶¶[0024]-[0035]).
We agree with Appellant. Paragraph [0031] of Appellant’s original
specification explicitly teaches adjusting the bias voltage between the source
(S) 310 and the well (CSN) 302, shown in FIG. 3, the value of the drain
current (Id) can be controlled. In other words, the value of the output current
of the transistor can be adjusted (i.e., increased or decreased) by varying the
value of the bias voltage of the semiconductor well, as described in
paragraph [0039] of Appellant’s original Specification.
For the reasons set forth above, we find error in the Examiner’s
“written description” rejection. Accordingly, we do not sustain the
Examiner’s “written description” rejection of claims 1-20.

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§ 103(a) Rejection of Claims 1-20 over Chandrakasan and Meng
The Examiner finds that Chandrakasan discloses a method of
controlling an output current of a transistor of a SOI type disposed in a
semiconductor well comprising most features of independent claim 1, except
for a P+ (heavily doped) contact region positioned within the semiconductor
well adjacent to a source, and the semiconductor well coupled to ground, via
an insulating layer, which are disclosed by FIG. 2 of Meng. FOA 3-4 (citing
Chandrakasan, transistors in circuit 1098, FIG. 1 and FIG. 6; and Meng,
FIG. 2). In addition, the Examiner further finds the wherein clause “a
threshold voltage of the transistor and the transistor output current in
response to a gate voltage are dependent upon and changed by adjustments
to the bias voltage” is an inherent characteristic of a transistor of a SOI type,
as evidenced, for example, in FIGS. 3A-3C of Teraoka, U.S. Patent No.
6,333,571. FOA 3 (emphasis added).
Appellant makes several arguments against the combination of
Chandrakasan and Meng, including:
(1) Chandrakasan discloses a complementary metal-
oxide semiconductor (CMOS) transistor pair having a triple-
well transistor structure, which is not equivalent to a single
transistor of Appellant’s claim 1, and, as such, the Examiner’s
reliance on the plurality of transistors to teach Appellant’s
single transistor is clear error (App. Br. 14-16 (citing
Chandrakasan, col. 4, ll. 20-22; col. 7, ll. 8-13, 19-21; col. 10,
ll. 6-12, 30-34; FIG. 1 and FIG. 6));

(2) Chandrakasan does not disclose that, when the
transistor is turned on, the transistor output current is changed
or adjusted by a bias voltage (App. Br. 17 (citing
Chandrakasan, FIG. 1 and FIG. 6));
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(3) Teraoka, U.S. Patent No. 6,333,571 does not
support the Examiner’s assertion that the “threshold voltage of
the transistor and the transistor output current in response to a
gate voltage are dependent upon and changed by adjustments to
the bias voltage” is an inherent characteristic of a transistor of a
SOI (App. Br. 18 (citing Teraoka, col. 2, ll. 34-38m, col. 9, ll.
60-61, col. 11, ll. 4-6; FIGS. 3A-3C)); and

(4) contrary to the Examiner’s assertion, Meng only
discloses that the substrate (56) is grounded and reference
numbers 52 and 54 are wells, but neither of which is coupled to
ground, via any insulating layer, and, as such, the Examiner’s
reliance upon the substrate (56) to teach the semiconductor well
recited in the claims is clear error. App. Br. 20-21 (citing Meng,
col. 2, ll. 47-48; col. 3, ll. 23-24).

We are not persuaded by Appellant’s arguments. First, a plurality of
transistors as disclosed by Chandrakasan also comprises a single transistor
such as Appellant’s claimed “transistor,” as correctly found by the
Examiner. Ans. 3. In addition, Chandrakasan also describes that such an IC
component can also be a single transistor or a pair of transistors. See
Chandrakasan, col. 2, ll. 34-35; and FIG. 1. Moreover, Chandrakasan
further describes that those transistors can be fabricated on a silicon-on-
insulator (SOI) wafer with buried gate structure as disclosed by Appellant.
See Spec., ¶[0039] (“[B]ecause of the use of a transistor formed inside a well
of the SOI (Silicon-On-Insulator) type, the value of the output current of the
transistor can be adjusted by varying the value of the bias voltage of the well
… and accordingly can be biased using positive voltage values, in contrast to
transistors of the standard type.”); see also Chandrakasan, col. 7, ll. 26-31;
and FIG. 1.
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Second, Chandrakasan discloses a method of controlling an output
current of a transistor, shown in FIG. 1 and FIG. 6, by way of adjusting both
(1) the supply voltages (Vdd, Vss) and (2) the threshold voltages applied to
semiconductor well 123 or 124 of the transistor, via the bias voltages (Vbp,
Vbn), to control power consumption. Ans. 4 (citing Chandrakasan, col. 10,
ll. 30-51; FIG. 1 and FIG. 6; also see col. 6, ll. 20-21; col. 7, ll. 32-55).
Third, and contrary to Appellant’s contention, the adjustment of the
transistor output current based on the bias voltage is an inherent
characteristic or function of a transistor of a SOI type in contrast to
transistors of standard type, as acknowledged by Appellant’s own
Specification. See Spec., ¶[0039]. As such, we agree with the Examiner
that Chandrakasan discloses the transistor output current is changed by
adjustments to the bias voltages. Ans. 5. Moreover, where Appellant’s
claimed “transistor” of a SOI type and prior art transistors of SOI type are
identical or substantially identical in structure, as shown in Appellant’s FIG.
3 and FIG. 1 of Chandrakansa, a prima facie case of obviousness has been
established. In re Best, 562 F.2d 1252 (CCPA 1977). Such a prima facie
case can only be rebutted by evidence showing that the prior art transistors
of SOI type do not necessarily possess the characteristics of Appellant’s
claimed transistor, which Appellant has not done in this case. Id. at 1255.
See also Titanium Metals Corp. v. Banner, 778 F.2d 775 (Fed. Cir. 1985).
Appellant’s attack on Teraoka, U.S. Patent No. 6,333,571, regarding
inherency is insufficient to do so here.
Fourth, and contrary to Appellant’s contention, Meng teaches that
semiconductor well 52 is coupled to ground, via an insulating layer 54, as
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shown in FIG. 2, and that contact region P+ in well 52 is adjacent to the
source terminal. Ans. 5 (citing Meng, FIG. 2).
For the reasons set forth above, we find the Examiner’s factual
findings regarding Chandrakasan and Meng are supported by preponderance
of evidence. We also agree with the Examiner’s conclusion that:
it would have been obvious to one having ordinary skill in the
art to coupled [sic] the substrate 121 of Chandrakasan et al. to
ground via insulating layer P+ and to add a P+ well contact
adjacent to Chandrakasan et al.’s source for the purpose of
reducing leakage current increasing speed.

FOA 3.
Accordingly, we sustain the Examiner’s obviousness rejection of
claims 1-20 over Chandrakasan and Meng.

§ 103(a) Rejection of Claims 1-20 over Koch, Chandrakasan and Meng
Appellant also contends that the Examiner erred in rejecting claims 1-
20 under 35 U.S.C. § 103(a) as being unpatentable over Koch in
combination with Chandrakasan and Meng. App. Br. 22-24. Because the
Examiner’s rejection of claims 1-20 over Chandrakasan and Meng is
sustained, we need not reach Appellant’s other arguments regarding Koch.
Accordingly, we also sustain the Examiner’s obviousness rejection of claims
1-20 for the same reasons discussed relative to Chandrakasan and Meng.
Nevertheless, we note that Koch discloses the same transistor of SOI type
disclosed in the instant Specification. See Koch, FIG. 1. Because Koch uses
the same transistor of SOI type, a preponderance of the evidence establishes
that one would have necessarily, i.e., inherently, adjusted the value of the
output current of the transistor by varying the value of the bias voltage of the
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well and, accordingly, would have been biased in the same manner as
described by Appellant’s Specification, ¶[0039]. See Koch, col. 4, ll. 12-48;
FIG. 1.

CONCLUSION
On the record before us, we conclude that the Examiner has erred in
rejecting claims 1-20 under 35 U.S.C. § 112, 1st paragraph, as failing to
comply with the written description requirement. However, we conclude
that the Examiner has not erred in rejecting: (1) claims 1-20 under 35 U.S.C.
§ 103(a) as being unpatentable over Chandrakasan and Meng; and (2) claims
1-20 under 35 U.S.C. § 103(a) as being unpatentable over Koch,
Chandrakasan, and Meng. Because we have affirmed at least one ground of
rejection with respect to each claim on appeal, the Examiner’s decision is
affirmed. See 37 C.F.R. § 41.50(a)(1).

DECISION
As such, we AFFIRM the Examiner’s final rejections of claims 1-20.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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