Ex Parte Belluomini et al

Patent Trial and Appeal Board

Nov 17, 2014

11776454 (P.T.A.B. Nov. 17, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/776,454 07/11/2007 Wendy Ann Belluomini AUS920030494US3 6796
45992 7590 11/18/2014
IBM CORPORATION (JVM)
C/O LAW OFFICE OF JACK V. MUSGROVE
2911 BRIONA WOOD LANE
CEDAR PARK, TX 78613
EXAMINER
NGO, CHUONG D
ART UNIT PAPER NUMBER
2193
MAIL DATE DELIVERY MODE
11/18/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte WENDY ANN BELLUOMINI, HUNG CAI NGO,
and JUN SAWADA
____________________

Appeal 2012-004060
Application 11/776,4541
Technology Center 2100
____________________

Before ST. JOHN COURTENAY III, THU A. DANG, and
LARRY J. HUME, Administrative Patent Judges.

HUME, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the Final
Rejection of claims 1–4, 8, 9, and 22. Appellants have previously canceled
claims 5, 6, and 10–21. The Examiner indicates claim 7 is directed to
allowable subject matter. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

1 According to Appellants, the real party in interest is International Business
Machines Corp. App. Br. 2.
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STATEMENT OF THE CASE2
The Invention
Appellants' invention generally relates to data processing systems,
more specifically to logic circuits which perform arithmetic functions, and
particularly multipliers that use Booth encoders. Spec. 1, ll. 5–7.
Exemplary Claims
Claims 1, 3, and 9, reproduced below, are representative of the subject
matter on appeal (formatting and emphases added to disputed limitations):
1. A fused Booth encoder multiplexer logic cell
comprising:
a logic circuit having
a plurality of operand input bits including
multiplier input bits and multiplicand input bits,
a dynamic node, and
a logic tree containing a plurality of logic
transistors,
each logic transistor in said logic tree having a gate
connected to one of the operand input bits and said logic
transistors being interconnected to carry out a Boolean function
according to a Booth encoding and selection algorithm to
produce a partial product bit for a multiplication operation at
the dynamic node in a single clock phase.

2 Our decision relies upon Appellants' Appeal Brief ("App. Br.," filed
Sept. 27, 2011); Reply Brief ("Reply Br.," filed Jan. 18, 2012); Examiner's
Answer ("Ans.," mailed Nov. 10, 2011); Final Office Action ("Final Act.,"
mailed Apr. 28, 2011); and the original Specification ("Spec.," filed
July 11, 2007).
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3. The fused Booth encoder multiplexer logic cell of
Claim 1 wherein:
the operand inputs bits include two multiplicand input
bits A(i..i+ 1) and three multiplier input bits C(i-l..i+1); and the
Boolean function which produces the partial product bit is
given by the expression

9. The fused Booth encoder multiplexer logic cell of
Claim 8 wherein a first source/drain junction in a first one of
said transistor stacks is connected to a second source/drain
junction in a second one of said transistor stacks.
Prior Art
The Examiner relies upon the following prior art as evidence in
rejecting the claims on appeal:
Bernstein et al.
("Bernstein")
US 6,404,236 B1 June 11, 2002
Campbell US 6,717,442 B2 Apr. 6, 2004
Qi US 7,024,445 B2 Apr. 4, 2006
Rejections on Appeal
R1. Claims 1–3 and 22 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over the combination of Qi and Bernstein. Ans. 4.
R2. Claims 4, 8, and 9 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over the combination of Qi, Bernstein, and Campbell.
Ans. 6.
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GROUPING OF CLAIMS
Based on Appellants' arguments (App. Br. 6–11), we decide Rejection
R1 of claims 1, 2, and 22 on the basis of representative claim 1. Claim 3,
argued separately under Rejection R1, stands alone.
Claim 9 in Rejection R2, argued separately, stands alone. We address
remaining claims 4 and 8 in Rejection R2, not argued separately, infra.
ISSUES AND ANALYSIS
We only consider those arguments actually made by Appellants in
reaching this decision, and we do not consider arguments which Appellants
could have made but chose not to make in the Briefs so that any such
arguments are deemed to be waived. 37 C.F.R. § 41.37(c)(1)(vii).
We disagree with Appellants' contentions with respect to claims 1–4,
8, 9, and 22, and we adopt as our own (1) the findings and reasons set forth
by the Examiner in the action from which this appeal is taken and (2) the
reasons and rebuttals set forth by the Examiner in the Examiner's Answer in
response to Appellants' Arguments. However, we highlight and address
specific findings and arguments regarding claims 1, 3, and 9 for emphasis as
follows.
1. Rejection R1 of Claims 1, 2, and 22
Issue 1
Appellants argue (App. Br. 6–10; Reply Br. 4–6) the Examiner's
rejection of claims 1, 2, and 22 under 35 U.S.C. § 103(a) as being obvious
over the combination of Qi and Bernstein is in error. These contentions
present us with the following issue:
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Did the Examiner err in finding the cited prior art combination teaches
or suggests a "fused Booth encoder multiplexer logic cell" with "a logic
circuit having . . . a plurality of logic transistors . . . interconnected to carry
out a Boolean function according to a Booth encoding and selection
algorithm to produce a partial product bit for a multiplication operation at
the dynamic node in a single clock phase," as recited in claim 1?
Analysis
Appellants contend the reference combination "fails to result in a
logic tree for a Booth encoder multiplexer which fuses the encoding and
selection functions to allow generation of a partial product bit in a single
clock phase." App. Br. 6. In particular, Appellants contend Qi does not
teach or suggest a "fused"3 circuit that carries out both Booth encoding and
selection functions in a single, integrated circuit over a single clock cycle,
but instead argues Qi discloses a conventional two-stage construction
requiring two clock cycles where Booth encoding must be completed in the
first clock cycle before the Booth selection in the second clock cycle. App.
Br. 6–7. Appellants argue their invention significantly improves
performance by computing a partial product bit at an evaluation node of a
logic tree in a single clock phase. App. Br. 7.

3 Although not explicitly defined by Appellants' Specification, the phrase
"fused . . . cell" appears to connote a logic cell in which two functions —
Booth encoding and Booth selection — are both carried out. Spec. 14,
ll. 16–18; see also Spec. 11, ll. 13–16. Appellants argue in this regard,
"[t]hose skilled in the art will understand that Appellants' circuit is
accordingly 'fused' because there is no multiplexer or selector stage which is
separately distinguishable from an encoder stage." App. Br. 7.
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We summarize Appellants' arguments cited above as follows: (1) the
cited art does not teach or suggest a single, integrated circuit logic circuit,
i.e., a "fused" circuit; and (2) the prior art does not teach or suggest carrying
out a Boolean function according to a Booth encoding and selection
algorithm in a single clock phase.
Argument (1)
With respect to the first argument, the Examiner finds, and we agree:
[In the] Qi reference, the Booth-encoder cells do not form a
column in a separate block but are combined with respective
Booth selector cells to form an array of partial product bit
generators . . . . Each partial product bit generator implements
the Boolean function of eqn.(5) . . . as clearly explained in the
rejection, [which] is clearly a Boolean function that produces
the partial product bit PPji based on a Booth encoding and
selection algorithm . . . .
Ans. 8–9 (citing Qi Figs. 3, 6, and 7A). The Examiner further finds Figure 6
of Qi teaches or at least suggests an implementation in a single circuit. Ans.
9. We agree. In the Reply, Appellants argue "[t]he critical point is that Qi
also has two separate blocks for Booth encoding and Booth selection . . . .
The encoding function is performed by blocks 190, 194 in Qi's Figure 8."
Reply Br. 4.
During examination, a claim must be given its broadest reasonable
interpretation consistent with the Specification, as it would be interpreted by
one of ordinary skill in the art. Because the applicant has the opportunity to
amend claims during prosecution, giving a claim its broadest reasonable
interpretation will reduce the possibility that the claim, once issued, will be
interpreted more broadly than is justified. In re Yamamoto, 740 F.2d 1569,
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1571 (Fed. Cir. 1984); In re Zletz, 893 F.2d 319, 321 (Fed. Cir. 1989)
("During patent examination the pending claims must be interpreted as
broadly as their terms reasonably allow."). In this case, Appellants' provide
no definition in their Specification, apart from arguing the functionality
performed, i.e., encoding and selection, that might contradict the Examiner's
broad but reasonable interpretation.
In this appeal, we find no compelling argument as to where the line
must be drawn in order to define a "circuit," or that a first circuit may not
contain another "circuit" therein. The mere fact Qi refers to Figures 8 and 9
in terms of "stages" (Qi col. 9, ll. 37 et seq.) does not preclude the
Examiner's broad but reasonable interpretation that Qi Figure 9 constitutes a
single circuit. We also note Appellants' arguments in this regard (App. Br. 6
et seq.; Reply Br. 4–5) are not commensurate with the scope of claim 1,
which recites "a logic circuit having a plurality [of elements]," and does not
recite a "single circuit," as argued.
As an additional matter of claim construction, we note the recitation
of "fused Booth encoder multiplexer logic cell" is only found in the
preamble of claim 1. See also Reply Br. 4–5. "Generally, the preamble does
not limit the claims." Allen Eng'g Corp. v. Bartell Indus., Inc., 299 F.3d
1336, 1346 (Fed. Cir. 2002). Nonetheless, the preamble may be construed
as limiting "if it recites essential structure or steps, or if it is 'necessary to
give life, meaning, and vitality' to the claim." Catalina Mktg. Int'l, Inc. v.
Coolsavings.com, Inc., 289 F.3d 801, 808 (Fed. Cir. 2002) (quoting Pitney
Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305 (Fed. Cir. 1999)).
A preamble is not regarded as limiting, however, "when the claim body
describes a structurally complete invention such that deletion of the
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preamble phrase does not affect the structure or steps of the claimed
invention." Catalina, 289 F.3d at 809. Furthermore, the preamble has no
separate limiting effect if, for example, "the preamble merely gives a
descriptive name to the set of limitations in the body of the claim that
completely set forth the invention." IMS Tech., Inc. v. Haas Automation,
Inc., 206 F.3d 1422, 1434–35 (Fed. Cir. 2000). See also Am. Med. Sys., Inc.
v. Biolitec, Inc., 618 F.3d 1354, 1359 (Fed. Cir. 2010).
In this case, we find the claim body describes a structurally complete
invention, and the preamble merely provides a descriptive name to a
limitation in the body of the claim, e.g., "Booth" encoding. Further, "fused"
is not further recited in the body of the claim, and need not be considered
further limiting.
In addition, without objective evidence to the contrary, we find simply
integrating known components is generally insufficient to establish
patentability. In re Larson, 340 F.2d 965, 968 (CCPA 1965) ("[T]he use of
a one piece construction instead of the structure disclosed in [the prior art]
would be merely a matter of obvious engineering choice.").4

4 Cf. Schenck v. Nortron Corp., 713 F.2d 782 (Fed. Cir. 1983) (Claims were
directed to a vibratory testing machine (a hard-bearing wheel balancer)
comprising a holding structure, a base structure, and a supporting means
which form “a single integral and gaplessly continuous piece.” Nortron
argued the invention is just making integral what had been made in four
bolted pieces. The court found this argument unpersuasive and held the
claims were patentable because the prior art perceived a need for
mechanisms to dampen resonance, whereas the inventor eliminated the need
for dampening via the one-piece gapless support structure, showing insight
that was contrary to the understandings and expectations of the art.). We
find no evidence of record to support such a finding in this appeal.
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On this record, Appellants have not persuaded us that the Examiner's
proffered combination of references would have been "uniquely challenging
or difficult for one of ordinary skill in the art." See Leapfrog Enters., Inc. v.
Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR Int'l
Co. v. Teleflex, Inc., 550 U.S. 398, 418 (2007)). Nor have Appellants
provided objective evidence of secondary considerations which our
reviewing court guides "operates as a beneficial check on hindsight."
Cheese Sys., Inc. v. Tetra Pak Cheese and Powder Systems, 725 F.3d 1341,
1352 (Fed. Cir. 2013). See also App. Br. 16 ("Evidence Appendix . . . No
evidence is being submitted with this appeal."). Accordingly, on this record,
we see no evidence of a long-felt need or other secondary considerations
which might otherwise rebut the Examiner's prima facie case of
obviousness.
Argument (2)
With respect to the second argument, the Examiner finds Qi Figure 10
illustrates the transmission gates implementing multiplexor 350 in Figure 9
do not require any clock input signal, thereby necessitating operation in the
same clock phase with the first section of the partial product bit generator of
Figures 8 and 9. Appellants disagree, as best exemplified in their Reply.
Reply Br. 5.
We agree with Appellants on this technical point, as Qi does not
explicitly disclose, teach, or suggest producing "a partial product bit for a
multiplication operation at the dynamic node in a single clock phase," as
recited in claim 1 (emphasis added). For us to find otherwise on this record
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would require speculation regarding all the technical details of Qi, which we
decline to do.
However, as a matter of claim construction, we note claim 1 merely
recites "logic transistors being interconnected . . . to produce a partial
product bit for a multiplication operation at the dynamic node in a single
clock phase" (emphasis added). We conclude such claim language
encompasses a statement of intended use, and not a positive recitation.
"[A]pparatus claims cover what a device is, not what a device does."
Hewlett-Packard Co. v.Bausch & Lomb Inc., 909 F.2d 1464, 1468 (Fed. Cir.
1990). In this case, we find the combination of Qi and Bernstein provides
the same structure as claimed.
Therefore, a question arises as to how much patentable weight, if any,
should be given to the contested limitation, because actual production of a
partial product bit in a single clock cycle is not positively recited. "An
intended use or purpose usually will not limit the scope of the claim because
such statements usually do no more than define a context in which the
invention operates." Boehringer Ingelheim Vetmedica, Inc. v. Schering-
Plough Corp., 320 F.3d 1339, 1345 (Fed. Cir. 2003). Although ''[s]uch
statements often . . . appear in the claim's preamble . . .'' (In re Stencel, 828
F.2d 751, 754 (Fed. Cir. 1987)), a statement of intended use or purpose can
appear elsewhere in a claim. Id.
Thus, giving claim 1 its broadest reasonable interpretation, the claim
merely requires a structure of interconnected transistors capable of
producing a partial product bit for a multiplication operation at the dynamic
node in a single clock phase. We find the combination of Qi and Bernstein
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teaches or at least suggests this capability, notwithstanding any potential
ambiguity in Qi's use of clock signals.
Accordingly, Appellants have not provided sufficient evidence or
argument to persuade us of any reversible error in the Examiner's reading of
the contested limitations on the cited prior art, or in the resulting legal
conclusion of obviousness. Therefore, we sustain the Examiner's
obviousness rejection under § 103 of independent claim 1, and claims 2 and
22, which fall therewith.
§ 103(a) Rejection R2 of Claims 4 and 8
In view of the lack of any substantive or separate arguments directed
to the obviousness Rejection R2 of claims 4 and 8 under § 103 (see App.
Br. 11), we sustain the Examiner's obviousness rejection of these claims, as
they fall with their respective independent claims. Arguments not made are
considered waived. See Hyatt v. Dudas, 551 F.3d 1307, 1314 (Fed. Cir
2008) ("When the appellant fails to contest a ground of rejection to the
Board, section 1.192(c)(7) [(now section 41.37(c)(1)(vii))] imposes no
burden on the Board to consider the merits of that ground of rejection . . . .
[T]he Board may treat any argument with respect to that ground of rejection
as waived."). Further, when Appellants do not separately argue the
patentability of dependent claims, the claims stand or fall with the claims
from which they depend. In re King, 801 F.2d 1324, 1325 (Fed. Cir. 1986);
In re Sernaker, 702 F.2d 989, 991 (Fed. Cir. 1983). Accordingly, we sustain
the rejection of claims 4 and 8.
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2. Rejection R1 of Claim 3
Issue 2
Appellants argue (App. Br. 10–11) the Examiner's Rejection R1 of
claim 3 under 35 U.S.C. § 103(a) as being obvious over the combination of
Qi and Bernstein is in error. These contentions present us with the following
issue:
Did the Examiner err in finding the cited prior art combination teaches
or suggests all limitations of claim 3 because the claim does not merely
recite generalized operand input bits, but instead recites a very specific
formula that carries out both Booth encoding and Booth selection for a
single logic tree, as recited in claim 3?
Analysis
Appellants contend Figure 7A of Qi "does not show a Boolean
function whose direct parameters are multiplicand and multiplier bits . . .
[instead, the] partial product bit equation is a function of the intermediate
signals (aai, sj) which reflects the fact that Qi's multiplexer has the 2-stage
construction as explained above [with respect to claim 1]." App. Br. 10–11.
The Examiner finds, and we agree, "[e]xpanding eqn. (5) as defined in
Eqns. (6)-(11) would clearly results in the same Boolean logic equation with
inputs being multiplicand and multiplier bits ai and bj as recited in claim 3."
Ans. 9. The Examiner continues by substituting the variables in equations
(6)–(11) into equation (5), and comparing the resulting equation with the
equation recited in claim 3. We agree with the Examiner's findings and legal
conclusion of obviousness, and note Appellants have not rebutted the
Examiner's findings in their Reply.
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Accordingly, Appellants have not provided sufficient evidence or
argument to persuade us of any reversible error in the Examiner's reading of
the contested limitations on the cited prior art, or in the resulting legal
conclusion of obviousness. Therefore, we sustain the Examiner's
obviousness rejection under § 103 of dependent claim 3.
3. Rejection R2 of Claim 9
Issue 3
Appellants argue (App. Br. 11) the Examiner's rejection of claim 9
under 35 U.S.C. § 103(a) as being obvious over the combination of Qi,
Bernstein, and Campbell is in error. These contentions present us with the
following issue:
Did the Examiner err in finding the cited prior art combination teaches
or suggests a fused Booth encoder multiplexer logic cell "wherein a first
source/drain junction in a first one of said transistor stacks is connected to a
second source/drain junction in a second one of said transistor stacks," as
recited in claim 9?
Analysis
Appellants contend "[n]one of Qi, Bernstein or Campbell describe a
source/drain junction in one transistor stack being connected to a
source/drain junction in another transistor stack." App. Br. 11.
In response, the Examiner provides a detailed mapping of the
limitations to the prior art with which we agree, and incorporate as our own
herein. See Ans. 7–8 and 10–11. We note Appellants do not rebut the
Examiner's detailed findings in their Reply.
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Accordingly, Appellants have not provided sufficient evidence or
argument to persuade us of any reversible error in the Examiner's reading of
the contested limitations on the cited prior art, or in the resulting legal
conclusion of obviousness. Therefore, we sustain the Examiner's
obviousness rejection under § 103 of dependent claim 9.
REPLY BRIEF
To the extent Appellants advance new arguments in the Reply Brief
(Reply Br. 4–6) not in response to a shift in the Examiner's position in the
Answer, we note that "[a]ny bases for asserting error, whether factual or
legal, that are not raised in the principal brief are waived." Ex parte Borden,
93 USPQ2d 1473, 1474 (BPAI 2010) (informative). Cf. with Optivus Tech.,
Inc. v. Ion Beam Appl'ns. S.A., 469 F.3d 978, 989 (Fed. Cir. 2006) ("[A]n
issue not raised by an appellant in its opening brief . . . is waived.").
CONCLUSION
The Examiner did not err with respect to the obviousness rejections of
claims 1–4, 8, 9, and 22 under 35 U.S.C. § 103(a) over the combinations of
prior art of record, and we sustain the rejections.
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DECISION5
We affirm the Examiner's decision rejecting claims 1–4, 8, 9, and 22.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2011).
AFFIRMED

msc

5 Although not before us on appeal, should there be further prosecution of
this application (including any review for allowance), we invite the
Examiner's attention to claim 1 to evaluate compliance under 35 U.S.C.
§ 101 in light of a recent Supreme Court decision concerning subject matter
eligibility (Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 134 S. Ct. 2347, 2358
(2014)), and the recently issued preliminary examination instructions on
patent eligible subject matter. See “Preliminary Examination Instructions in
view of the Supreme Court Decision in Alice Corporation Pty. Ltd. v. CLS
Bank International, et al.,” Memorandum to the Examining Corps,
June 25, 2014. It appears claim 1 may merely encompass an abstract idea in
the form of a Boolean function according to a Booth encoding and selection
algorithm, so that its subject matter eligibility under § 101 may be in
question. See also Ex parte Gutta, 93 USPQ2d 1025, 1031 (BPAI 2009)
(precedential) (holding that system claim 14 directed to a mathematical
algorithm was non-statutory under § 101 despite reciting a memory and
processor).