Ex Parte Baskaran et alDownload PDFPatent Trial and Appeal BoardJun 25, 201310911726 (P.T.A.B. Jun. 25, 2013) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 10/911,726 08/05/2004 Narayanan Baskaran 129250-002033/US 8972 32498 7590 06/25/2013 CAPITOL PATENT & TRADEMARK LAW FIRM, PLLC P.O. BOX 1995 VIENNA, VA 22183 EXAMINER LEE, CHUN KUAN ART UNIT PAPER NUMBER 2181 MAIL DATE DELIVERY MODE 06/25/2013 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte NARAYANAN BASKARAN, RICHARD J. DIPASQUALE, JEFFREY R. TOWNE, and GARY A. TURNER ____________ Appeal 2011-001881 Application 10/911,726 Technology Center 2100 ____________ Before JOSEPH F. RUGGIERO, SCOTT R. BOALICK, and MIRIAM L. QUINN, Administrative Patent Judges. QUINN, Administrative Patent Judge. DECISION ON APPEAL Appeal 2011-001881 Application 10/911,726 2 Appellants appeal under 35 U.S.C. § 134(a) (2002) from a final rejection of claims 1, 3, 4, 6, 9-14, 18, 21, 23, 24, 26-29, and 31. Claims 2, 5, 7, 8, 15-17, 19, 20, 22, 25, 30, 32, and 33 have been cancelled. We have jurisdiction under 35 U.S.C. § 6(b). We AFFIRM. STATEMENT OF THE CASE The invention relates to a digital delay buffer with both, a fast processing, small capacity memory section and a slow processing, large capacity memory section. Spec. Abstract. 1 According to Appellants, the use of two memory sections allows the buffer to generate an aligned data stream with n-bit block level latencies from a plurality of delayed data portions, even if one of the portions is subjected to an undue delay. Id. Details of the appealed subject matter, with disputed claim language emphasized, are recited in illustrative representative claims 1 and 18, reproduced below from the Claims Appendix of the Appeal Brief: 1. A digital data stream delay buffer comprising: a fast processing, small capacity (FPSC) memory section operable to receive one or more delayed data portions of an original data stream; a slow processing, large capacity (SPLC) memory section operable to receive one or more delayed data portions of the original data stream; and 1 References to Appellants’ Specification (“Spec.”) are directed to the Specification filed on November 15, 2004. Appeal 2011-001881 Application 10/911,726 3 a control section connected to each of the memory sections and operable to, detect a delay associated with each of the received delayed data portions, allow the FPSC memory section to output an aligned data stream, having substantially the same alignment as an alignment associated with the original data stream, formed from the one or more delayed data portions without using data stored in the SPLC memory section, provided none of the detected delays exceeds a time period equivalent to a time period at which a memory capacity of the FPSC memory section reaches a maximum, and allow the FPSC memory section to output the aligned data stream using a selected, variable amount of data stored in the SPLC memory section when one or more of the detected delays exceeds the time period wherein both the FPSC and SPLC memory sections contain at least some identical data portions of the original data stream. 18. A digital data stream delay buffer comprising: a slow processing, large capacity (SPLC) memory section operable to receive one or more delayed data portions of an original data stream, and to output a selected, variable amount of data representing the one or more portions when one or more of the received portions has been subjected to a delay that exceeds a time period equivalent to a time period at which a memory capacity of an fast processing, small capacity (FPSC) memory section reaches a maximum. As evidence of unpatentability of the claimed subject matter, the Examiner relies on the following reference at pages 4 to 14 of the Answer: Lu US 6,473,815 B1 Oct. 29, 2002 Appeal 2011-001881 Application 10/911,726 4 The Examiner also relies on Applicants’ Admitted Prior Art (“AAPA”). The Examiner provides the following grounds of rejection, of which Appellants seek review: (1) Claims 18 and 31 stand rejected under 35 U.S.C. § 112, second paragraph, as being indefinite in that they fail to point out what is included or excluded by the claim language. (Ans. 4-5); and (2) Claims 1, 3, 4, 6, 9-14, 18, 21, 23, 24, 26-29, and 31 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over AAPA and Lu (Ans. 5-14). ANALYSIS We have reviewed the Examiner’s rejection in light of Appellants’ contention. Further, we have reviewed the Examiner’s response to Appellants’ arguments. Appellants did not argue separate patentability of dependent claims 3, 4, 6, 9-13, 23, 24, and 26-28. Therefore, except for our ultimate decision, these claims are not discussed further herein. Appellants raise three dispositive issues on appeal as discussed further below. ISSUE 1: SECTION 112, 2 ND PARAGRAPH REJECTION Appellants contend that the Examiner erred in rejecting claims 18 and 31 under 35 U.S.C. § 112, 2 nd paragraph, because the claims do not omit “essential steps.” App. Br. 6-7. In particular, Appellants contend that claims 18 and 31 do not recite the Fast Processing Small Capacity (“FPSC”) Appeal 2011-001881 Application 10/911,726 5 memory, and that inclusion of the FPSC memory is not required because the Specification describes that sometimes the FPSC memory is needed and other times both the FPSC memory and the Slow Processing Large Capacity (“SPLC”) memory are needed. Id. The Examiner responds that the claims must recite the FPSC memory because Appellants’ Specification describes that it is always used to generate an aligned data stream. Ans. 15. The issue for us to decide is whether claims 18 and 31 include the FPSC, and if they do not, whether such omission renders the claims indefinite for failure to distinctly point out the invention. Determining the scope of the claims is an issue of claim construction. During examination proceedings, we determine claim scope by giving the claims their broadest reasonable interpretation consistent with the specification. See In re Hyatt, 211 F.3d 1367, 1372 (Fed. Cir. 2000). We do not read limitations out of the claims as “a claim construction analysis must begin and remain centered on the claim language itself . . . .” Innova/Pure Water, Inc. v. Safari Water Filtration Systems, Inc., 381 F.3d 1111, 1116 (Fed. Cir. 2004). Having considered the claim language of claim 18, we find that the FPSC memory section is positively recited in that claim, albeit as part of the recitation of the SPSC memory (“when one or more of the received portions has been subjected to a delay that exceeds a time period equivalent to a time period at which a memory capacity of an fast processing, small capacity (FPSC) memory section reaches a maximum”). In claim 31, the FPSC memory section is also positively recited as part of the outputting step limitation (using same language as that of claim 18). The inclusion of the FPSC is consistent with the Specification, which describes that the delay Appeal 2011-001881 Application 10/911,726 6 buffers of the invention include the use of both the FPSC memory section and the SPLC memory section. See Spec. ¶ [0010]-[0011]. Therefore, we cannot agree with Appellants’ contention that claims 18 and 31 do not include the FPSC memory. To do otherwise belies the claim language itself. Accordingly, because we conclude that the language of claims 18 and 31 recites an FPSC memory, we do not sustain the Examiner’s rejection of claims 18 and 31 under 35 U.S.C. § 112, 2 nd paragraph. ISSUE 2: SECTION 103 REJECTION OF CLAIMS 1 AND 21. Appellants next contend that the Examiner erred in rejecting independent claims 1 and 21 as obvious over Lu and Appellants’ Admitted Prior Art (“AAPA”) because Lu does not disclose that “both the FPSC and SPLC memory sections contain at least some identical data portions of the original data stream” [hereinafter the “identical data portions” limitation]. App. Br. 11-12. Appellants argue that while Lu’s queues store data from the same data stream, the data stored in each queue comes from different parts of the data stream. App. Br. 12. That is, the data stored in one of Lu’s queues is different from, i.e. not identical to, the data stored in another of Lu’s queues. The issue for us to decide is whether the Examiner erred in determining that the combination of Lu and the AAPA discloses the identical data portions limitation. We are not persuaded that the Examiner so erred. The identical data portions limitation is capable of two interpretations. The first, which is the one Appellants propose, involves the FPSC and SPLC Appeal 2011-001881 Application 10/911,726 7 memory section each storing portions of data, where some of those portions are identical to each other, i.e., some of the data stored in the FPSC and SPLC memories is the same. See App. Br. 12. The second interpretation, which is the one adopted by the Examiner, involves the FPSC and SPLC memories storing data portions that are identical to the original data stream. See Ans. 17. That is, the FPSC memory stores data that is identical to some of the portions of the original data stream, while the SPLC memory also stores data that is identical to some of the portions of the original data stream. However, the data stored in FPSC and SPLC memories is not necessarily identical to each other. The claim language is broad enough to bear both interpretations, which are both reasonable in light of the Specification. Therefore, we find that the Examiner’s position adopting the second interpretation is not unreasonable. In light of that interpretation, we also agree with the Examiner’s findings that Lu teaches the high class queue storing data received from the data stream and the medium class queue storing data received from the data stream. Ans. 17-18. Accordingly, the combination of those teachings in Lu with the AAPA, which discloses the known use of a SPLC memory section, teaches: high class queue (e.g. FPSC memory section) that contain[s] at least some identical portions of the original data stream and the medium class queue (e.g. SPLC memory section) that contains at least some identical data portions of the original data stream when the high class queue is full (e.g. overflow). Ans. 18. Appeal 2011-001881 Application 10/911,726 8 Appellants next contend that Lu teaches away from the combination of Lu and AAPA because Lu teaches dropping overflow data instead of attempting to store it. App. Br. 12-13. We do not agree with Appellants’ contention. Lu teaches placing overflow data in one of the other queues, which are not full. Lu, Abstract; col. 5, ll. 12-14. That Lu teaches dropping as an alternative when all other queues have reached a threshold is not teaching away from storing the overflow data. “A reference may be said to teach away when a person of ordinary skill, upon reading the reference, would be discouraged from following the path set out in the reference, or would be led in a direction divergent from the path that was taken by the applicant.” In re Gurley, 27 F.3d 551, 553 (Fed. Cir. 1994). We are not persuaded that a person of ordinary skill in the art, upon reading Lu in its entirety, would be led away from storing overflow data in another queue as taught by Lu. Consequently, we sustain the Examiner’s rejection of claims 1 and 21 under 35 U.S.C. § 103(a) over Lu and AAPA. ISSUE 3: SECTION 103 REJECTION OF CLAIMS 14, 18, 29, AND 31. Lastly, Appellants contend that the Examiner erred in rejecting independent claims 14, 18, 29, and 31 for obviousness over Lu and the AAPA because Lu does not disclose or suggest the following limitations [hereinafter the “delay” limitations]: (a) “allow[ing] an FPSC memory section to output the aligned data stream using a selected, variable amount of data stored in the Appeal 2011-001881 Application 10/911,726 9 SPLC memory section when one or more of the detected delays exceeds the time period,” as recited in claims 14 and 29; 2 and (b) “output[ting] a selected, variable amount of data representing the one or more portions when one or more received portions has been subjected to a delay that exceeds a time period equivalent to a time period at which a memory capacity of an fast processing, small capacity (FPSC) memory section reaches a maximum,” as recited in claims 18 and 31. More specifically, Appellants argue that “Lu simply permits data to be stored in another queue when one queue is full without regards to a delay time period, among other things.” App. Br. 15. The issue for us to decide is whether the Examiner erred in determining that the combination of Lu and the AAPA teaches the delay limitations. We are not persuaded that the Examiner so erred. First, the Examiner finds, and we agree, that Lu teaches detecting the delay associated with the received data packets. See Ans. 12. For example, Lu teaches, in column 2, lines 41-55, a method to determine the head or tail packet delay of the received packets. Furthermore, we concur with the Examiner that Lu teaches that if received data exceeds a delay time period associated with the high class queue, the delayed received data is stored in the middle class queue instead. Ans. 20. For example, Lu teaches 2 We note that independent claims 1 and 21 appear to recite similar limitations, but were not grouped by Appellants in this argument. See App. Br. 14-15. Accordingly, we do not include these claims in this argument even if the scope of the disputed language is similar to that of claims 1 and 21. See 37 C.F.R. § 41.37(c)(1)(vii)(2011). Appeal 2011-001881 Application 10/911,726 10 determining that the queue is full (reaching a maximum) when the head or tail delay exceeds a delay threshold. Lu, col. 2, ll. 53-55; col. 6, ll. 42-46. That is, contrary to Appellants’ argument, Lu teaches determining whether to store data in a specific queue based on the detected delay exceeding the delay threshold for the specific class queue. In short, Appellants have not shown sufficient evidence that the Examiner erred in finding that the combination of Lu and the AAPA teaches the delay limitation. Accordingly, we sustain the Examiner’s rejection of claims 14, 18, 29, and 31 under 35 U.S.C. § 103(a). CONCLUSION In light of our interpretation of claims 18 and 31 including the FPSC limitation, we reverse the Examiner’s decision to reject claims 18 and 31 under 35 U.S.C. § 112, second paragraph. Further, we conclude that Appellants have not shown error in the Examiner’s findings and conclusions that the subject matter recited in independent claims 1, 14, 18, 21, 29, and 31 is obvious over Lu and the AAPA. Therefore, we sustain the rejection of claims 1, 14, 18, 21, 29, and 31 under 35 U.S.C. § 103(a), as well as dependent claims 3, 4, 6, 9-13, 23, 24, and 26-28 which depend from claims 1 and 21. See 37 C.F.R. § 41.37(c)(1)(vii)(2011). DECISION We AFFIRM the Examiner’s decision to reject claims 1, 3, 4, 6, 9-14, 18, 21, 23, 24, 26-29, and 31. Appeal 2011-001881 Application 10/911,726 11 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv)(2011). AFFIRMED ELD Copy with citationCopy as parenthetical citation