Ex Parte Baskakov et al

Patent Trial and Appeal Board

Aug 5, 2016

12900271 (P.T.A.B. Aug. 5, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO.
12/900,271
36378 7590
VMWARE, INC,
DARRYL SMITH
FILING DATE
10/07/2010
08/09/2016
3401 Hillview Ave.
PALO ALTO, CA 94304
FIRST NAMED INVENTOR
YuryBASKAKOV
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
A460 7461
EXAMINER
LI,ZHUOH
ART UNIT PAPER NUMBER
2133
NOTIFICATION DATE DELIVERY MODE
08/09/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ipteam@vmware.com
ipadmin@vmware.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte YURY BASKAROV, ALEXANDER GARTHWAITE,
and JESSE POOL
Appeal2015-002089 1
Application 12/900,271
Technology Center 2100
Before JEAN R. HOMERE, HUNG H. BUI, and
AARON W. MOORE, Administrative Patent Judges.
HOMERE, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants seek our review under 35 U.S.C. § 134(a) of the
Examiner's Final Rejection of claims 1-3, 7, 8, and 17-28. App. Br. 1.
Claims 10-16 have been withdrawn from consideration. Claims App 'x.
Claims 4--6 and 9 have been objected to as being dependent upon a rejected
base claim, but would otherwise be allowable if rewritten in independent
form to include the limitations of the base claim, and any intervening claims.
Final Act. 7. We have jurisdiction under 35 U.S.C. § 6(b).
1 Appellants identify the real party in interest as VMware, Inc. App. Br. 3.
Appeal2015-002089
Application 13/900,271
We reverse.
Appellants 'Invention
Appellants' invention is directed to a method and system for
improving the memory performance in a virtual machine by loading there-
into metadata of a memory page just in time for immediate use (i.e. when the
memory page is needed). Spec. i-f 5. In particular, upon detecting that (1)
the page signature of the memory page has been added to the metadata, and
(2) a flag is set to indicate that contents of the memory page need updating,
the metadata is loaded into the memory without loading the contents of the
memory page. Id. at i-fi-1 5---6.
Illustrative Claim
Independent claim 1 is illustrative, and reads as follows:
1. A method of loading memory pages allocated to virtual machines,
compnsmg:
determining a page signature of a memory page;
adding the page signature to metadata of the memory page and setting
a flag in the metadata to indicate that contents of the memory page need to
be updated; and
loading the metadata of the memory page into memory without
loading the contents of the memory page.
Jordan et al.
Schneider
Prior Art Relied Upon
US 7,383,415 B2
US 7,711,921 B2
Rejection on Appeal
2
June 3, 2008
May4, 2010
Appeal2015-002089
Application 13/900,271
Claims 1-3, 7, 8, and 17-28 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over the combination of Schneider and Jordan.
ANALYSIS
Appellants argue that Jordan's disclosure of delaying a demapping
operation to invalidate the translation in the TLB does not teach loading
metadata of a memory page into memory without loading the contents of the
memory page. App. Br. 8. According to Appellants, Jordan's enqueuer
demap operation, which involves loading an address into a register to delay
the demap operation, has nothing to do with loading metadata in memory
without the contents of the memory page. Id. at 9 (citing Jordan 18: 12-23).
This argument is persuasive.
The Examiner correctly finds that, when the update bit is set, and a
demap operation is required, loading the demap operation in an address
space identifier (ASI) until no more TLB updates are pending will result in
delaying the demap operation. Ans. 4 (citing Jordan Fig. 4). However, we
do not agree with the Examiner that such delay of the demap operation will,
in tum, result in loading metadata in the ASI queue without loading the
contents of the data page. Although enqueuing the demap operations in the
ASI buffer causes the addresses thereof to be loaded in a memory, the
enqueued demap operations are not metadata of a memory page. Instead,
they are requests to invalidate identified translations in the TLB. Jordan
13:40-52. At best, the combination of Jordan and Schneider would result in
a memory page allocated to a virtual machine wherein the metadata thereof
includes a signature value, and an update flag indicating whether no updates
are pending such that enqueued demapping operations can be completed to
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Appeal2015-002089
Application 13/900,271
thereby invalidate identified entries in a TLB table. Because Appellants
have shown at least one reversible error in the Examiner's rejection, we need
not reach Appellants' remaining arguments. We, therefore, agree with
Appellants that the proposed combination of references does not teach the
disputed limitation. Accordingly, we do not sustain the obviousness
rejection of representative claim 1, or the rejections of claims 2, 3, 7, 8, and
17-28, which recite commensurate limitations.
DECISION
We reverse the Examiner's rejection of claims 1-3, 7, 8, and 17-28.
REVERSED
4