Ex Parte Barnes et al

Patent Trial and Appeal Board

Oct 31, 2012

09999881 (P.T.A.B. Oct. 31, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
09/999,881 10/31/2001 Brian C. Barnes 2162.056800/TT4088 8630
10742 7590 10/31/2012
GLOBALFOUNDRIES INC.
c/o Williams, Morgan & Amerson
10333 Richmond , Suite 1100
Houston, TX 77042
EXAMINER
DADA, BEEMNET W
ART UNIT PAPER NUMBER
2435
MAIL DATE DELIVERY MODE
10/31/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte BRIAN C. BARNES, GEOFFREY S. STRONGIN,
and RODNEY W. SCHMIDT
____________________

Appeal 2011-000332
Application 09/999,881
Technology Center 2400
____________________

Before: KALYAN K. DESHPANDE, JASON V. MORGAN, and
TREVOR JEFFERSON, Administrative Patent Judges.

JEFFERSON, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF CASE
Appellants appeal under 35 U.S.C. § 134 from a rejection of claims 1-
20. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
INVENTION
The invention is directed to a method and apparatus for physical
address-based security to provide secure memory access in computer
systems by performing a virtual memory access. Spec. 2:6-9; 4:22 - 5:5.
Claims 1 and 8, reproduced below with disputed limitations in italics, are
illustrative of the claimed subject matter:
1. A method, comprising:
executing a software object;
establishing a security level for said software object;
performing a multi-table memory access using at least
one of said security levels; and
executing a function of said object.

8. A method, comprising:
executing a software object;
establishing a security level for said software object;
establishing a secondary table;
receiving a memory access request based upon said
executing of said software object;
determining at least one security level that corresponds to
a segment in said secondary table;
verifying a match between an execution security level to
a security level associated with a segment being accessed in
response to an execution of said software object;
determining a virtual memory address based upon said
secondary table in response to a match between said execution
security level and said security level associated with said
segment being accessed;
locating a physical memory location corresponding to
said virtual memory address; and
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accessing a portion of a memory based upon locating said
physical memory location.

REJECTIONS
Claims 1-3, 12-14 and 16 stand rejected under 35 U.S.C §102(b) as
being anticipated by Covey (US 4,926,476; May 15, 1990). Ans. 3.
Claims 4-11, 15 and 17-20 stand rejected under 35 U.S.C §103(a) as
being unpatentable over Covey and Clifton (US 5,469,556, Nov. 21, 1995).
Ans. 4.

ISSUES
Did the Examiner err in finding that Covey discloses “executing a
software object” and “performing a multi-table memory access using at least
one of said security levels” as recited in claim 1?
Did the Examiner err in finding that the combination of Covey and
Clifton teaches or suggests “establishing a secondary table” as recited in
claim 8?
Did the Examiner err in concluding that it would have been obvious to
combine the teachings and suggestions of Covey and Clifton?

CLAIM GROUPING
Appellants argue independent claim 1 as representative of claims 1-3,
12-14 and 16 (App. Br. 6-10), and independent claim 8 as representative of
claims 8-11 and 17-20 (App. Br. 10-13). Appellants make no separate
arguments, however, for dependent claims 4-7 (App. Br. 13-14), which stand
or fall with their respective independent claims. We select claim 1 as
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representative of claims 1-7, 12-14 and 16 and claim 8 as representative of
claims 8-11 and 17-20.

ANALYSIS
Claim 1
Appellants contend that Covey fails to anticipate claim 1 because
Covey teaches source operands and not software objects as recited in claim
1. App. Br. 7. Appellants also contend that sensitivity levels or associating
a label with data that software is given access to in Covey are not equivalent
to establishing a security level for a software object. App. Br. 8. According
to Appellants, “Covey merely discloses providing security levels for data,
there is no teaching or suggestion in Covey that relates to establishing a
security level for a software object, as called for in claim 1.” App. Br. 8.
Appellants also argue that Covey fails to teach or disclose multi-table
memory access as recited in claim 1. App. Br. 9.
The Examiner found that “Covey teaches executing a software object
(i.e., executing a software program/process/instruction, column 5, line 9),
and establishing a security level for the software object (i.e., the executed
software objected is provided a security level by computing sensitivity level
for all its operands thereby the instant runtime software
object/program/process/instruction is provided with a security level)
[column 5, line 9-19 and column 6, lines 4-10].” Ans. 7.
We agree with the Examiner’s findings. The Examiner found that a
software object is an instance of a software process or execution. Ans. 7-8.
Covey discloses that a security level is established for “[e]ach program
which is allowed to execute on the CPU.” Covey col. 6, ll. 4-5; see also Ans.
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7. Such programs are the instance of a software process that are executed to
access memory at various security levels. See Ans. 7-8.
Appellants also assert that multipage table and storage blocks are not
the same as teaching multi-table memory access as claimed. Appellants
contend that “[w]hile Covey may show more than one page table 40, Covey
simply discloses a single-table memory access through one of the page
tables 40.” App. Br. 10. Thus, Covey is unlike the multi-table memory
access found in Appellants’ Specification, col. 13, ll. 4-13.
The Examiner interpreted “multi-table memory access…as access to
portions of a memory that are divided in blocks/sections (i.e., one divided
section of a memory would be equivalent to a table and multiple sections
would be equivalent to multiple tables).” Ans. 8.
We agree with the Examiner that Covey discloses a multi-table
memory access as each memory is divided in multiple labeled storage
blocks, where a “labeled storage block is defined as an area of data storage
with which a single sensitivity level is associated.” Covey, col. 4, ll. 25-46;
see also Ans. 8. We find that a labeled storage block constitutes a table and
Covey discloses multiple storage blocks defined by their sensitivity levels.
Appellants’ citations to “non-limiting” examples of multi-table memory in
Appellants’ specification (App. Br. 5, 6) are not commensurate in scope with
the claim language, which broadly recites “a multi-table memory access”
and is not limited to the examples in Appellants’ specification. See In re
Am. Acad. Of Sci Tech. Ctr., 367 F.3d 1359, 1369 (Fed. Cir. 2004).
In light of the foregoing, the Examiner did not err in finding that
Covey discloses “executing a software object” and “performing a multi-table
memory access using at least one of said security levels” as recited in claim
1. Accordingly, we sustain the Examiner’s 35 U.S.C. § 102(b) rejection of
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claim 1. We also sustain the Examiner’s 35 U.S.C. § 102(b) rejection of
independent claims 12, 13 and dependent claims 2-7 and 14 and 16, which
Appellants do not argue separately. See App. Br. 6-10.
Claim 8
Appellants contends that Covey and Clifton fail to teach “establishing
a secondary table” as recited in claim 8. App. Br. 12, 15. Appellants argue
that “a secondary table is distinct from multiple tables of the same type” and
cite example references to secondary tables found in the Specification. App.
Br. 12.
With respect to the secondary table limitation, Appellants non-
limiting illustrative descriptions of “a secondary table” as being hierarchical
are not persuasive. See App. Br. 12. The Examiner correctly found that
Covey teaches multiple tables that are associated with different sensitivity
levels. Ans. 9; Covey, col. 4, ll. 25-46. We agree with the Examiner’s
findings that secondary table includes having more than one table. See Ans.
9. Furthermore, the different security levels for storage blocks disclosed in
Covey, col. 4, ll. 25-46, that serve as the first and second tables, fall within
the “non-limiting” illustrative example found in Appellants’ specification
that describe secondary tables as those stored at high security levels. Spec.
11:19-20; see App. Br. 11-12 (describing illustrative examples of secondary
tables found in Appellants’ specification).
Appellants also contend that the Examiner failed to specify the
relevant teachings in the prior art to maintain a prima facie case of
obviousness for claim 8. App. Br. 12 (stating that the Examiner failed to
identify each limitation of claim 8 in Covey and merely cites the same
passage for each limitation).
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We disagree with Appellants’ argument. The Examiner has pointed to
specific portions of Covey and has made findings with respect to claim 8
limitations. Ans. 4-6 (citing elements of Covey for each claim 8 limitation),
8-9 (discussing same). Appellants have not shown error with respect to
those findings. Indeed, Appellants’ Reply Brief fails to respond to the
Examiner’s findings and merely repeats the argument presented for claim 1
that Covey fails to teach multi-table memory. Reply 6.
Finally, we do not agree with Appellants’ contention that Covey and
Clifton would not be combined by one of ordinary skill in the art. App. Br.
14-15, Reply 6-7. The Supreme Court in KSR Int’l Co. v. Teleflex Inc., 550
U.S. 398 (2007), rejected the rigid requirement of a teaching or suggestion
or motivation to combine known elements in order to show obviousness. Id.
at 415. We find that the Examiner has provided an articulated line of
reasoning with a rational underpinning to support the conclusion of
obviousness with respect to the proposed combination of Covey and Clifton.
See Ans. 10 (stating that “both Covey and Clifton teach controlling access to
memory” and that “one of ordinary skill in the art at the time of the
applicant’s invention” would combine Clifton and Covey for “efficient
execution of instructions by using a virtual memory space”).
For the foregoing reasons, the Examiner did not err in combining the
teachings and suggestions of Covey and Clifton and finding that they
disclose establishing “a secondary table” as recited in claim 8. Accordingly,
we sustain the Examiner’s 35 U.S.C. § 103(a) rejection of claims 4-11, 15
and 17-20.
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DECISION
For the above reasons, the Examiner’s rejection of claims 1-20 is
affirmed.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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